在 VHDL 中添加无法编译? [英] Addition in VHDL not compiling?
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问题描述
我知道这是一个相当臭名昭著的话题,但通常的解决方案似乎都不起作用..
I know this is a fairly notorious topic, but none of the usual solutions seem to be working..
这是给出错误的行:
ppl_stage_cnt <= ppl_stage_cnt + 1;
这是我得到的错误(来自 xst):
Here's the error I get (from xst):
Line 89: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
这里有更多信息可以放在上下文中:
Here's more information to put it in context:
signal ppl_stage_cnt : std_logic_vector(log2(ppl)-1 downto 0);
pplstage_cnt: process ( clk )
begin
if rising_edge( clk ) then
if rst = '1' or ei = '1' or li = '1' then
ppl_stage_cnt <= (others => '0');
else
ppl_stage_cnt <= ppl_stage_cnt + 1;
end if;
end if;
end process;
我尝试过的其他事情:
ppl_stage_cnt <= std_logic_vector(to_unsigned(ppl_stage_cnt, log2(ppl)) + 1);
ppl_stage_cnt <= std_logic_vector(unsigned(ppl_stage_cnt) + '1');
推荐答案
尝试
ppl_stage_cnt <= UNSIGNED(ppl_stage_cnt) + 1;
来源:http://objectmix.com/vhdl/190708-how-do-perform-std_logic_vector-addition-using-ieee-numeric_std.html,std_logic_vector operator
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