如何在Makefile中使用Bash参数替换? [英] How to use Bash parameter substitution in a Makefile?

问题描述

我有以下Makefile，我想在其中使用

I've the following Makefile where I'd like to use Bash parameter substitution syntax as below:

SHELL:=/bin/bash
Foo=Bar
all:
  @echo ${Foo}
  @echo ${Foo/Bar/OK}

但是它不能按预期方式工作，因为第二个echo命令的输出为空:

However it doesn't work as expected, as the output of the second echo command is empty:

$ make
Bar
(empty)

尽管直接在shell中调用时效果很好:

Although it works fine when invoking in shell directly:

$ Foo=Bar; echo ${Foo/Bar/OK}
OK

如何在Makefile中使用以上语法?

How can I use the above syntax in Makefile?

推荐答案

如果您想让Shell扩展变量，则必须使用Shell变量，而不是make变量. ${Foo/Bar/OK}是一个从字面上称为Foo/Bar/OK的make变量.

If you want the shell to expand the variable you have to use a shell variable, not a make variable. ${Foo/Bar/OK} is a make variable named literally Foo/Bar/OK.

如果要使用shell变量替换，则必须将该值分配给shell变量:

If you want to use shell variable substitution you'll have to assign that value to a shell variable:

all:
        Foo='$(Foo)'; echo $${Foo/Bar/OK}

请注意，我们使用双美元$$来转义美元符号，以使make不会尝试扩展美元符号.

Note that we use the double-dollar $$ to escape the dollar sign so that make doesn't try to expand it.

我强烈建议您在确定规则有效之前，不要在规则中添加@.这是我看到的最常见的单个错误；如果人们只是不使用@，他们可以看到make正在调用命令，那么他们将更好地了解make的工作原理.

I strongly recommend you don't add @ to your rules until you're sure they work. It's the single most common mistake I see; if people would just not use @ they could see the command make is invoking, and then they would better understand how make works.

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