强制Makefile中先决条件的顺序 [英] forcing order of prerequisites in Makefiles

问题描述

我有一个第三方makefile，我希望在先构建另一个自定义目标(T2)之前不要构建目标(T1).通常，这可以通过将T2设为T1的先决条件来实现.但是，T1在其规则之一中使用$ ^ ..因此，通过添加先决条件，我最终破坏了构建……我所拥有的是这样的:

I have a third party makefile, and I'd like one of the targets (T1) to not be built until another, custom target (T2) is built first. Normally, this would be accomplished by making T2 a prerequisite of T1. BUT, T1 uses the $^ in one of its rules.. so, by adding the prerequisite, I end up breaking the build... What I have is this:

T1: x y z T2
    $(MAKE) -j $^;
    # fails because T2 should not be passed to the make!!!

.PHONY: T2

T2:
    #do some linking and prep for T1

是否有很好的方法来确保T2在T1之前运行? (注意:上面的示例实际上有点简化了.T1实际上是Linux内核makefile中的vmlinux目标，因此重写它不仅很困难，而且使代码不可移植.而且，我之前不能运行T2由于其他一些依赖性，在内核上调用make.)

Is there a good way to ensure that T2 is run before T1? (Note: the above example is actually simplified by a bit. T1 is actually the vmlinux target within the Linux kernel makefile, so rewriting it is not only difficult, it makes the code non-portable. Also, I can't run T2 before calling make on the kernel due to some other dependencies).

推荐答案

将T2作为仅订购先决条件:

T1: x y z | T2
    $(MAKE) -j $^;
    # Make will run the T2 rule before this one, but T2 will not appear in $^

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