Makefile，模式规则和目录 [英] Makefile, Pattern-Rules and Directories

问题描述

我想为编译器编写一个(gmake)makefile，与gcc不同，该编译器将所有输出文件放入特定目录中.不幸的是，这种行为无法更改.

I want to write a (gmake) makefile for a compiler that - unlike gcc - puts all output files into a specific directory. Unfortunately this behavior cannot be changed.

我的来源在多个目录中.如何编写一个模式规则，让我可以编译源代码.

My sources are in multiple directories. How do I write a pattern-rule that lets me compile the sources.

好吧，这还不清楚.这是一个例子.我的资料来源可能是这样的:

Okay, that's a bit unclear. Here is an example. My sources look may like this:

./folder1/foo.c
./folder2/bar.c

，输出文件将像这样结束:

and the output files will end up like this:

./obj/foo.obj
./obj/bar.obj

我的规则汇编源代码应该是什么样子?

How should my rule to compile my sources look like?

%.obj : %.c 
   $(COMPILER) -c $< 

将不起作用.

有什么想法吗?我想避免对每个源文件使用隐式规则...

Any ideas? I'd like to avoid an implicit rule for each source file...

推荐答案

从我的一些Makefile中提取:

Extracted from some Makefile of mine:

OBJS := $(sort $(patsubst %.cpp,$(OBJECT_DIRECTORY)/%.o,$(patsubst %.c,$(OBJECT_DIRECTORY)/%.o,$(notdir $(SRCS)))))

OBJECT_DIRECTORY指向对象目录，而SRCS是源文件列表(您甚至可以使用$(wildcard)填充).

Where OBJECT_DIRECTORY points to the object directory and SRCS is the list of source files (which you can even populate using $(wildcard)).

然后在Makefile中，我有:

Then in the Makefile, I have:

define define_compile_rules
$(OBJECT_DIRECTORY)/%.o: $(1)%.c
  @echo " + Compiling '$$<'"
  @mkdir -p $$(@D)
  $(CC) $$(CFLAGS) -o $$@ -c $$<
endef

$(foreach directory,$(sort $(dir $(SRCS))),$(eval $(call define_compile_rules,$(directory))))

请参见 $(eval)函数.

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