使用内存映射的I/O管理缓存 [英] Managing cache with memory mapped I/O

问题描述

我有一个关于内存映射io的问题. 假设有一个内存映射的IO外设，其值正在由CPU读取.读取后，该值将存储在高速缓存中.但是内存中的值已由外部IO外设更新. 在这种情况下，CPU将如何确定缓存已失效，这种情况下的解决方法是什么?

I have a question regarding memory mapped io. Suppose, there is a memory mapped IO peripheral whose value is being read by CPU. Once read, the value is stored in cache. But the value in memory has been updated by external IO peripheral. In such cases how will CPU determine cache has been invalidated and what could be the workaround for such case?

推荐答案

这与平台密切相关.实际上，有两种不同的情况.

That's strongly platform dependent. And actually, there are two different cases.

案例1..内存映射的外围设备.这意味着对某些范围的物理内存地址的访问将路由到外围设备.没有实际的RAM.为了控制缓存，例如x86具有MTRR(内存类型范围寄存器")和PAT(页面属性表").它们允许在特定范围的物理内存上设置缓存模式.在正常情况下，映射到RAM的内存范围是回写式可缓存，而映射到外围设备的内存范围是 uncacheable .

Case #1. Memory-mapped peripheral. This means that access to some range of physical memory addresses is routed to peripheral device. There is no actual RAM involved. To control caching, x86, for example, has MTRR ("memory type range registers") and PAT ("page attribute tables"). They allow to set caching mode on particular range of physical memory. Under normal circumstances, range of memory mapped to RAM is write-back cacheable, while range of memory mapped to periphery devices is uncacheable. Different caching policies are described in Intel's system programming guide, 11.3 "Methods of caching available". So, when you issue read or write request to memory mapped peripheral, CPU cache is bypassed, and request goes directly to the device.

案例2. DMA.它允许外围设备异步访问RAM.在这种情况下，DMA控制器与任何CPU都一样，并且平等地参与高速缓存一致性协议.其他CPU的高速缓存可以看到来自外围设备的写请求，并且高速缓存行将无效或被新数据更新.其他CPU的缓存也可以看到读取请求，并且数据是从缓存而不是从主RAM返回的. (这只是一个示例:实际实现取决于平台.例如，SoC通常不保证外围设备<-> CPU具有很强的缓存一致性.)

Case #2. DMA. It allows peripheral devices to access RAM asynchronously. In this case, DMA controller is no different from any CPU and equally participates in cache coherency protocol. Write request from periphery is seen by caches of other CPUs, and cache lines are either invalidated or are updated with new data. Read request also is seen by caches of other CPUs and data is returned from cache rather than from main RAM. (This is only an example: actual implementation is platform dependent. For example, SoC typically do not guarantee strong cache coherency peripheral <-> CPU.)

在两种情况下，缓存问题也存在于编译器级别:编译器可能会将数据值缓存在寄存器中.这就是为什么编程语言有一些禁止这种优化的方法的原因:例如，C中的volatile关键字.

In both cases, the problem of caching also exists at compiler level: complier may cache data values in registers. That's why programming languages has some means of prohibiting such optimization: for example, volatile keyword in C.

这篇关于使用内存映射的I/O管理缓存的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！