内存映射I的缓存行为/ O [英] Cache behaviour of memory-mapped I/O

问题描述

有谁知道CPU缓存行为，类型（例如，不可缓存的写入合并）被分配到的文件备份的，内存映射现代x86系统的I / O？有什么方法来检测是哪种情况，并有可能覆盖默认行为？

Windows和Linux感兴趣的主要操作系统。

解决方案

施加到地址空间区域高速缓存策略通常独立于操作系统并且只在型地址空间页后面设备的依赖。事实上operatng系统无任何缓存策略适用于任何内存区域，但incorectly分配的缓存策略可以降低系统性能或损纸系统逻辑可言。

有三种缓存策略：

1. 展开缓存（回写）。
   施加到映射到主存储器（RAM）的物理地址空间。用于提高内存子系统performnce的性能。这种装置的主要特性是它的状态只能通过软件来改变，并且可以实现仅软件。该内存映射文件执行使用全缓存，因为它们完全实现通过从磁盘读取的文件块，并把它放在内存中，然后把这个块（可能修改）回磁盘软件（操作系统）。


2. 直写式高速缓存。
   施加到像内存映射视频存储器的输出设备。这种装置的主要特性是它的状态可以仅通过软件改变，但改变必须对设备立即生效。根据此策略，写入到存储器映射的IO设备的寄存器数据将被放置在同时两个位置：在高速缓存和设备。但是，当该数据读操作将被启动，数据将被从未经expencive访问设备缓存捕获。


3. 禁用缓存。
   施加到几乎所有的IO设备，因为写入到存储器映射的IO设备寄存器必须有立即的短跑运动员，并从存储器映射的IO设备的寄存器读取必须从设备返回到读取实际的数据。如果高速缓存将被应用到存储器映射的IO设备，则需要两个负面影响将被引入：
   
   
   
   1. 写入到存储器映射的IO设备寄存器时便会推迟到时刻时高速缓冲存储器控制器将决定刷新高速缓存线与写入的数据。作为结果，司机就无法知道什么时候writen到设备的命令生效。
   
   
   2. 从内存映射IO设备寄存器中读取数据可以被缓存。与从相同存储器映射的IO设备寄存器读取后续数据可以从缓存返回从设备不是实际的数据，但过时的数据。由于这个原因，这将是很难驱动捕捉设备的实际状态。
   
   

由于这样的事实，通过该软件可以指定缓存策略的方式是只取决于处理器相同的算法可以在任何操作系统被应用。
最简单的方法是捕获CR3寄存器的内容，并用它找到合适你想知道，检查PCD和PWT标志该缓存策略的地址页表项。但这种方式是不完整的，因为有可能影响缓存其他一些功能（例如，高速缓存可以完全上CR0禁用，参见MTRR，PAT）的

Does anyone know which type of CPU cache behaviour (e.g. uncacheable write-combining) is assigned to file-backed, memory-mapped I/O on modern x86 systems? Is there any way to detect which is the case, and possibly override the default behaviour?

Windows and Linux are the main operating systems of interest.

解决方案

Caching policy applied to the address space region is generally operating system independent and depend only on type of device behind the address space page. In fact operatng system is free to apply any caching policy to any memory region, but incorectly assigned caching policy can reduce system performance or broke system logic at all.

There are three caching policies:

1. Full caching (write-back). Applied to the physical address space mapped to the main memory (RAM). Used to increase performance of memory subsystem performnce. The main property of such devices is that it state can be changed only by software and can effect only software. The memory mapped files implementation use full caching because they implemented completely by software (operating system) that read file chunk from disk and place it memory and then put this chunk (possibly modified) back to disk.
2. Write-through caching. Applied to the output devices like memory-mapped video-memory. The main property of such devices is that it state can be changed only by software, but the change must have immediate effect on device. According to this policy, data written to the memory-mapped IO device register will be placed in two places concurrently: in cache and in device. But when the data read will be initiated, data will be captured from the cache without expencive access to the device.
3. Disabled caching. Applied to the almost all IO device, because the writing to the memory-mapped IO device register must have immediate effec and reading from the memory-mapped IO device register must return to the reader actual data from the device. If caching will be applied to memory-mapped IO device, then two negative effects will be introduced:
   1. The writing to the memory-mapped IO device register wil be delayed until the moment when cache controller will decide to flush cache line with written data. As result, driver won't be able to know when the command writen to the device will take effect.
   2. The reading data from the memory-mapped IO device register can be cached. And subsequent data read from the same memory-mapped IO device register can return not actual data from the device, but outdated data from the cache. Due to this, it will be hard to driver to capture actual state of the device.

Due to the fact that the way by which software can specify caching policy is only processor dependent the same algorithm can be applied in any operating system. The simplest way is to capture the content of CR3 register, and using it locate the Page Table Entry appropriate to the address which caching policy you want to know and check the PCD and PWT flags. But this way isn't complete because there are few other features that can affect caching (for example, caching can be completely disabled on CR0, see also MTRR, PAT).

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