DMA上下文中的缓存一致性问题 [英] Cache coherence issues in a DMA context

问题描述

假定CPU在x + 50位置修改了该值，并且没有将其刷新回主存储器(写回).

Suppose the CPU modifies the value in location x+50 and does not flush it back to main memory(write-back).

同时，设备启动从x到x + 100的DMA读取请求.

Meanwhile, a device launches a DMA read request from x to x+100.

在那种情况下，如何通知CPU刷新脏缓存行?

In that case, how the CPU is informed to flush back the dirty cache line?

推荐答案

DMA电路通常直接与主内存协同工作而不涉及CPU(这是主要思想，它可以使CPU从执行I/O的工作中解放出来.在硬件的其他位置完成，从而节省了CPU周期).因此，您确实可能遇到了缓存一致性问题. Microsoft建议刷新I/O缓冲区使用DMA时.

The DMA circuitry often works directly with the main memory without involving the CPU (and that's the main idea, to free the CPU from doing I/O that can be done elsewhere in the hardware and thus save CPU cycles). So, you may indeed run into cache coherency problems. Microsoft recommends flushing I/O buffers when using DMA.

但是某些系统确实支持CPU和DMA电路之间的高速缓存一致性协议，就像多处理器系统中CPU之间的缓存一致性协议一样.最终的答案取决于实际的硬件.

But some systems do support cache coherency protocols between CPUs and DMA circuits much like between CPUs in multiprocessor systems. The ultimate answer depends on the actual hardware.

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