为什么可以将MemoryBarrier实现为对xchg的调用? [英] why can MemoryBarrier be implemented as a call to xchg?

问题描述

http://msdn.microsoft.com/zh-CN/library/windows/desktop/ms684208(v=vs.85).aspx ，MemoryBarrier的实现是对xchg的调用.

on msdn http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208(v=vs.85).aspx, MemoryBarrier is implemented as a call to xchg.

// x86

FORCEINLINE
VOID
MemoryBarrier (
    VOID
    )
{
    LONG Barrier;
    __asm {
        xchg Barrier, eax
    }
}

在软件开发人员手册"中找不到某些资料. 请告诉我原因.

I can't find some material in "Software Developer's Manual". please tell me the reason.

推荐答案

摘自Intel 64 and IA-32 Architectures软件开发人员手册，第3卷:系统编程指南"

From Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3: "System Programming Guide"

8.2.5增强或减弱内存排序模型"

8.2.5 "Strengthening or Weakening the Memory-Ordering Model"

多处理器系统中的同步机制可能取决于 基于强大的内存排序模型.在这里，程序可以使用锁定 指令，例如XCHG指令或LOCK前缀，以确保 对内存执行读-修改-写操作 原子地.锁定操作通常类似于I/O操作 在中，他们等待所有之前的说明完成并等待 所有缓冲的写操作都会耗尽内存(请参见第8.1.2节总线" 锁定").

Synchronization mechanisms in multiple-processor systems may depend upon a strong memory-ordering model. Here, a program can use a locking instruction such as the XCHG instruction or the LOCK prefix to ensure that a read-modify-write operation on memory is carried out atomically. Locking operations typically operate like I/O operations in that they wait for all previous instructions to complete and for all buffered writes to drain to memory (see Section 8.1.2, "Bus Locking").

从8.1.2开始:

相对于所有其他内存，锁定操作是原子的 操作和所有外部可见事件. 仅提取指令 和页表访问可以传递锁定的指令.已锁定 指令可用于同步一个处理器写入的数据 并由另一个处理器读取.

Locked operations are atomic with respect to all other memory operations and all externally visible events. Only instruction fetch and page table accesses can pass locked instructions. Locked instructions can be used to synchronize data written by one processor and read by another processor.

对于P6系列处理器，锁定的操作会序列化所有 出色的加载和存储操作(即等待它们执行 完成).对于Pentium 4和Intel Xeon也适用此规则 处理器，只有一个例外.加载弱引用的操作 有序内存类型(例如WC内存类型)可能不是 序列化.

For the P6 family processors, locked operations serialize all outstanding load and store operations (that is, wait for them to complete). This rule is also true for the Pentium 4 and Intel Xeon processors, with one exception. Load operations that reference weakly ordered memory types (such as the WC memory type) may not be serialized.

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