多核汇编语言是什么样的? [英] What does multicore assembly language look like?

问题描述

例如，曾经有段时间要编写x86汇编程序，您将获得说明将EDX寄存器的值加载为5"，递增EDX"寄存器等说明.

Once upon a time, to write x86 assembler, for example, you would have instructions stating "load the EDX register with the value 5", "increment the EDX" register, etc.

对于具有4个内核(甚至更多)的现代CPU，在机器代码级别上看起来是否像有4个独立的CPU(即，是否只有4个不同的"EDX"寄存器)?如果是这样，当您说增加EDX寄存器"时，由什么决定增加哪个CPU的EDX寄存器? x86汇编器中现在有"CPU上下文"或线程"概念吗?

With modern CPUs that have 4 cores (or even more), at the machine code level does it just look like there are 4 separate CPUs (i.e. are there just 4 distinct "EDX" registers) ? If so, when you say "increment the EDX register", what determines which CPU's EDX register is incremented? Is there a "CPU context" or "thread" concept in x86 assembler now?

内核之间的通信/同步如何工作?

How does communication/synchronization between the cores work?

如果您正在编写操作系统，则通过硬件公开什么机制以允许您计划在不同内核上的执行?这是一些特殊的特权指令吗?

If you were writing an operating system, what mechanism is exposed via hardware to allow you to schedule execution on different cores? Is it some special priviledged instruction(s)?

如果您正在为多核CPU编写优化的编译器/字节码VM，那么您需要特别了解x86，以使其生成可在所有内核上高效运行的代码?

If you were writing an optimizing compiler/bytecode VM for a multicore CPU, what would you need to know specifically about, say, x86 to make it generate code that runs efficiently across all the cores?

对x86机​​器代码进行了哪些更改以支持多核功能?

What changes have been made to x86 machine code to support multi-core functionality?

推荐答案

这不是问题的直接答案，而是对注释中出现的问题的答案.本质上，问题是硬件为多线程操作提供了什么支持.

This isn't a direct answer to the question, but it's an answer to a question that appears in the comments. Essentially, the question is what support the hardware gives to multi-threaded operation.

尼古拉斯·弗林特(Nicholas Flynt)正确，至少关于x86.在多线程环境(超线程，多核或多处理器)中， Bootstrap线程(通常是处理器0中的内核0中的线程0)开始从地址0xfffffff0获取代码.所有其他线程都在称为 Wait-for-SIPI 的特殊睡眠状态下启动.作为其初始化的一部分，主线程通过APIC向WFS中的每个线程发送一个特殊的处理器间中断(IPI)，称为SIPI(启动IPI). SIPI包含该线程应从中开始获取代码的地址.

Nicholas Flynt had it right, at least regarding x86. In a multi threaded environment (Hyper-threading, multi-core or multi-processor), the Bootstrap thread (usually thread 0 in core 0 in processor 0) starts up fetching code from address 0xfffffff0. All the other threads start up in a special sleep state called Wait-for-SIPI. As part of its initialization, the primary thread sends a special inter-processor-interrupt (IPI) over the APIC called a SIPI (Startup IPI) to each thread that is in WFS. The SIPI contains the address from which that thread should start fetching code.

此机制允许每个线程从不同的地址执行代码.所需要的就是为每个线程建立自己的表和消息传递队列提供软件支持.操作系统使用那些进行实际的多线程调度.

This mechanism allows each thread to execute code from a different address. All that's needed is software support for each thread to set up its own tables and messaging queues. The OS uses those to do the actual multi-threaded scheduling.

就实际的程序集而言，如Nicholas所写，对于单线程或多线程应用程序，程序集之间没有区别.每个逻辑线程都有自己的寄存器集，因此编写:

As far as the actual assembly is concerned, as Nicholas wrote, there's no difference between the assemblies for a single threaded or multi threaded application. Each logical thread has its own register set, so writing:

mov edx, 0

只会为当前正在运行的线程更新EDX.无法使用单个汇编指令在另一个处理器上修改EDX.您需要某种系统调用来要求OS告诉另一个线程运行将更新其自己的EDX的代码.

will only update EDX for the currently running thread. There's no way to modify EDX on another processor using a single assembly instruction. You need some sort of system call to ask the OS to tell another thread to run code that will update its own EDX.

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