＆是什么QUOT;多芯QUOT;汇编语言是什么样子？ [英] What does "multicore" assembly language look like?

问题描述

曾几何时，写x86汇编，比如，你将有指示，指出加载EDX与价值5寄存器，递增EDX登记等。

Once upon a time, to write x86 assembler, for example, you would have instructions stating "load the EDX register with the value 5", "increment the EDX" register, etc.

随着现代的CPU有4个内核（甚至更多），在机器code级它只是看起来像有4个独立的CPU（即在那里只是4个不同的EDX寄存器）？如果是这样，当你说递增EDX注册，是什么决定了CPU的EDX寄存器递增？是否有一个CPU上下文或x86汇编线程的概念呢？

With modern CPUs that have 4 cores (or even more), at the machine code level does it just look like there are 4 separate CPUs (i.e. are there just 4 distinct "EDX" registers) ? If so, when you say "increment the EDX register", what determines which CPU's EDX register is incremented? Is there a "CPU context" or "thread" concept in x86 assembler now?

如何通信/芯工作之间的同步？

How does communication/synchronization between the cores work?

如果你正在写一个操作系统，什么机制是通过硬件接触，让您安排在不同的内核执行？它是一些特殊指令具有优越的（S）？

If you were writing an operating system, what mechanism is exposed via hardware to allow you to schedule execution on different cores? Is it some special priviledged instruction(s)?

如果你正在写一个优化编译器/字节code VM为多核CPU，你会需要知道具体有关，也就是说，86使它产生的所有核高效运行code？

If you were writing an optimizing compiler/bytecode VM for a multicore CPU, what would you need to know specifically about, say, x86 to make it generate code that runs efficiently across all the cores?

已经做了哪些修改x86机器code支持多核心功能？

What changes have been made to x86 machine code to support multi-core functionality?

推荐答案

这是不是直接回答这个问题，但它是一个问题的答案出现在评论的问题。从本质上讲，问题是什么支持硬件给予多线程操作。

This isn't a direct answer to the question, but it's an answer to a question that appears in the comments. Essentially, the question is what support the hardware gives to multi-threaded operation.

尼古拉斯·弗林特做得正确，至少对86。在多线程环境（超线程多核心或支持多处理器），在的引导线的（通常在核心0处理器0线程0）启动获取从地址 0xfffffff0 。所有其他线程称为一个特殊的睡眠状态下启动的等待换SIPI 的。作为其初始化的一部分，主线程发送一个特殊的处理器间中断（IPI）以上称为SIPI（启动IPI）到处于WFS每个线程APIC。该SIPI包含从该线程应该开始获取code的地址。

Nicholas Flynt had it right, at least regarding x86. In a multi threaded environment (Hyper-threading, multi-core or multi-processor), the Bootstrap thread (usually thread 0 in core 0 in processor 0) starts up fetching code from address 0xfffffff0. All the other threads start up in a special sleep state called Wait-for-SIPI. As part of its initialization, the primary thread sends a special inter-processor-interrupt (IPI) over the APIC called a SIPI (Startup IPI) to each thread that is in WFS. The SIPI contains the address from which that thread should start fetching code.

该机制允许每个线程从不同的地址执行code。所有这一切需要的是每个线程建立自己的表和邮件队列的软件支持。操作系统使用的的的做实际的多线程调度。

This mechanism allows each thread to execute code from a different address. All that's needed is software support for each thread to set up its own tables and messaging queues. The OS uses those to do the actual multi-threaded scheduling.

至于实际装配而言，尼古拉斯写道，有一个单线程还是多线程应用程序的组件之间没有什么区别。每个逻辑线程都有自己的寄存器组，这样写：

As far as the actual assembly is concerned, as Nicholas wrote, there's no difference between the assemblies for a single threaded or multi threaded application. Each logical thread has its own register set, so writing:

mov edx, 0

将只更新 EDX 为当前运行的线程的。有没有办法修改 EDX 上使用单个汇编指令另一个处理器。你需要某种形式的系统调用要求操作系统来告诉另一个线程来运行code，将更新自己的 EDX 。

will only update EDX for the currently running thread. There's no way to modify EDX on another processor using a single assembly instruction. You need some sort of system call to ask the OS to tell another thread to run code that will update its own EDX.

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