由多个1位ALU组成4位ALU [英] Making a 4-bit ALU from several 1-bit ALUs

问题描述

我正在尝试将几个1位ALU合并为一个4位ALU。我对如何在VHDL中实际执行此操作感到困惑。这是我使用的1位ALU的代码：

I'm trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using:

component alu1 -- define the 1 bit alu component
  port(a, b: std_logic_vector(1 downto 0);
  m: in std_logic_vector(1 downto 0);
  result: out std_logic_vector(1 downto 0));
end alu1;

architecture behv1 of alu1 is
begin
  process(a, b, m)
  begin
   case m is
     when "00" =>
        result <= a + b;
      when "01" =>
        result <= a + (not b) + 1;
      when "10" =>
        result <= a and b;
      when "11" =>
        result <= a or b;
    end case
  end process
end behv1

我假设我将alu1定义为较大实体alu4的组成部分，但是如何将它们绑在一起？

I am assuming I define alu1 as a component of the larger entity alu4, but how can I tie them together?

推荐答案

您甚至会问这个问题。 VHDL合成器非常有能力推断您喜欢的任何加法器。您只需输入所需内容即可。

Interesting you would even ask that question. VHDL synthesizers are quite capable of inferring any adder you like. You can just type what you need:

use ieee.numeric_std.all;
...
signal r : unsigned(3 downto 0);
signal a : unsigned(2 downto 0);
signal b : unsigned(2 downto 0);
signal c : unsigned(2 downto 0);
...
r  <=  a + b + c;

然后您可以切片 r 需求：

result  <=  std_logic_vector(r(2 downto 0));

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