64位ALU输出在TestBench波上显示出高阻抗 [英] 64-bit ALU outputs are showing high impedance on TestBench waves

问题描述

我必须制作一个64位ALU，该ALU接收A和B 64位输入，一个进位输入并输出64位结果以及一个1位进位.还有一个5位功能选择FS.FS [0]控制B是否反转(使用2to1多路复用器).F [1]对A执行相同的操作.FS[4:2]确定哪个操作(加，减，逻辑运算等)使用8to1多路复用器.下面是ALU和Testbench的代码.

I have to make a 64 Bit ALU that takes in A and B 64-bit inputs, a carry_in input and outputs a 64bit result along with a 1-bit carry_out. There is also a 5 bit function-select FS. Where FS[0] controls whether B is inverted or not (using a 2to1 mux.) F[1] does the same for the A. And FS[4:2] determines which operation (Adding, subtracting, logical operations, etc) using an 8to1 Mux. Below is the code for the ALU and Testbench.

我很确定我的测试平台很好，ALU的所有单独组件也都不错.我对实例化并连接所有输入/输出的顶层不太自信.是什么导致波形中的高阻抗?

I'm pretty sure my testbench is good and so is all the separate components for the ALU. I'm not too confident about my top-level where I instantiate and connect all the inputs/outputs. What is causing the high impedance in the waveform?

module ALU(A, B, FS, cin, cout, result); 
input [63:0] A, B;
input [4:0] FS;
input cin;
output cout;
output  [63:0] result;


eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 1'b0, 1'b0, FS[4:2], result);

adder u6 (firstoutA, secoutB, cin, sum, cout);

firstmux u1 (A, !A, FS[1], firstoutA);

secmux u2 (B, !B, FS[0], secoutB);

Alu_shifter u5 (A, left, right);


endmodule 
//--------------------------------------------------------------------------------//
//These are the two muxes to split into input and inverted input A,B
module firstmux(a, nota, firstS, firstoutA);
input [63:0] a, nota;
input firstS;
output reg [63:0] firstoutA;

always @(a or nota or firstS) 

begin

case(firstS)

0 : firstoutA = a;
1 : firstoutA = nota; 
default : firstoutA = 1'bx;

endcase
end

endmodule
//<><><><><><><>//
module secmux(b, notb, secS, secoutB);
input [63:0] b, notb;
input secS;
output reg [63:0] secoutB;

always @(b or notb or secS) 

begin

case(secS)

0 : secoutB = b;
1 : secoutB = notb; 
default : secoutB = 1'bx;

endcase
end

endmodule
//--------------------------------------------------------------------------------//


//This is the Shifter Blocks
module Alu_shifter (shiftA, right, left); //This shifter block shifts the A input once right or left
  input [63:0] shiftA;
  output [63:0] right;
  output [63:0] left;
  
  shift_right w1 (    //instantiate right shifter block
  .a_R(shiftA),  
  .R(right)
  );
  
  shift_left w2 (   //instantiate left shifter block
  .a_L(shiftA),
   .L(left)
  );
  
endmodule
////////><><><><><><><><><><><><><><><///////
module shift_right (a_R, R); // right shifter block
input [63:0] a_R;
output [63:0] R;
assign R = a_R >> 1;  //shift A right once (shift in a 0)
 endmodule


module shift_left (a_L, L);  //left shifter block
input [63:0] a_L;
output [63:0] L;
assign L = a_L << 1; //shift A left once (shift in a 0)
endmodule
//End shifter blocks (3 total modules)
//----------------------------------------------------//////////////////////
//This is the Adder that Adds A, B and cin
module adder(addA, addB, nic, sum, cout);
input [63:0] addA, addB;
input nic;
output [63:0] sum;
output cout;

assign {cout, sum} = addA + addB + nic;


endmodule

//----------------------------------------------------//////////////////////
//This is the 8to1 Mux that decides which operation is put forward
module eight_one_mux(D0, D1, D2, D3, D4, D5, D6, D7, S, out);
input [63:0] D0, D1, D2, D3, D4, D5, D6, D7;
input [2:0] S;
output reg [63:0] out;

always @(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S) 

begin

case(S)

0 : out = D0; //And
1 : out = D1; //Or
2 : out = D2; //Adder
3 : out = D3; //xor
4 : out = D4; //lefter
5 : out = D5; //righter
6 : out = D6; //GND
7 : out = D7; //GND
default : out = 1'bx;

endcase
end

endmodule
////////////-------------------------------////////////////////////////////

module ALU_tb();

reg [63:0] A, B;
reg [4:0] FS;
reg cin;

wire cout;
wire [63:0] result;


     
     ALU dut (
     .A(A),
     .B(B),
     .FS(FS),
     .cin(cin),
     .cout(cout),
     .result(result)
                    );


initial begin
A = 8'b11001100;
B = 8'b11001101;
FS = 5'b01101;
cin = 1;
end

always
#5 cin <= ~cin;

always begin
#5
A <= A + 1;
B <= B + 2;
#5;
end

initial begin
#100 $finish;
end
endmodule
```

推荐答案

首先，您需要为模块之间的连接定义信号( wire ).例如，您有 left 和 right 作为 Alu_shifter 模块的输出，它们已连接到 firstmux 和 secmux 模块；但是，它们没有在您的顶层模块中定义.您应该将以下信号定义添加到您的topmodule中:

First you need to define signals (wire) for connections between modules. For example, you have left and right as outputs of Alu_shifter module and they are connected to firstmux and secmux modules; however, they are not defined in your top module. You should add following signal definitions to your topmodule:

wire [63:0] left,right;
wire [63:0] firstoutA;
wire [63:0] secoutB;
wire [63:0] sum;

此外， eight_one_mux 模块采用八个64位输入.但是，您将它们的最后两个设置为 1'b0 .您应该将它们更改为 64'b0 ，如下所示.

Also, eight_one_mux module takes eight 64-bit inputs. However, you set the last two of them as 1'b0. You should change them to 64'b0 as below.

eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 64'b0, 64'b0, FS[4:2], result);

最后，！A 不会反转 A 的所有位(与 B 相同).它应用归约运算并生成一个1位信号(并且 firstmux 模块在其第二个输入端口中期望有64位信号).

Finally, !A does not invert all bits of A (same for B). It applies a reduction operation and generates a 1-bit signal (and firstmux module expects a 64-bit signal in its second input port).

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