有时在Verilog中可以互换使用输入和输出端口时，输入端口的确切标准是什么? [英] What is the exact criteria for an inout port, when sometimes inout and output ports can be interchangeably used in Verilog?
问题描述
在以下模块中，理想情况是宽度，宽度和宽度. start应该是inout端口，而不是输出端口.
In the below module, ideally cnt, width & start should be inout port, instead of output port.
但是我尝试将这些端口用作输出端口，但我仍然能够运行它而没有任何错误.那么inout和output端口可以在Verilog中互换使用吗?
But I tried with those ports as output ports and still I am able to run it without any error. So can inout and output ports be used interchangeably in Verilog?
如果否，那么确切的标准是什么，必须使用inout端口(在这种情况下不能使用输出端口)?
If no, then what is the exact criteria, where inout port must be used (output port can't be used in that case)?
module (clk, rst, cnt, start, width, signal);
input clk, rst, signal;
output reg [11:0] cnt, width;
output reg start;
always @(posedge clk or negedge rst)
begin
if(~rst)
begin
cnt <= 0;
start = 0;
width <= 'h271;
end
else
begin
if(signal)
begin
width <= (start) ? width : 'h271;
start = 1;
end
cnt <= (start) ? (cnt + 1) : cnt;
end
end
endmodule
注意-我知道，使用inout端口，我需要修改代码，因为inout端口不能是reg类型.但是我在这里只问端口类型.
Note - I know, that with inout ports, I need to modify the code, as inout ports can't be of reg type. But I am here asking about just type of ports only.
推荐答案
在Verilog中，端口方向基本上是建议性的，并且在SystemVerilog中并没有改变.这是一个历史问题，与Verilog XL(第一个Verilog模拟器)如何使端口崩溃有关.基本上，一切都是进场.编写'95 LRM时，基本上记录了这种现有行为.在1364-2005年，该值在12.3.8中显示为
Port direction is basically advisory in Verilog, and this hasn't changed in SystemVerilog. This is a historical isue, and is related to how Verilog XL (the first Verilog simulator) did port collapsing; basically, everything is an inout. when the '95 LRM was written this existing behaviour was basically documented. In 1364-2005 this appears in 12.3.8 as
被声明为输入(输出)但用作输出(输入)或inout的端口可能被强制为inout.如果不 强制为inout，必须发出警告.
A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout. If not coerced to inout, a warning has to be issued.
实际上，所有内容都以inout结尾，您可能会或可能不会收到警告.因此，您几乎可以在模拟器中执行任何操作，但是linter或合成器应该为您处理任何逻辑连接错误(如果没有，则毫无用处).以下各节中还有其他特定的非定向规则-input和inout端口必须是net类型，依此类推.
In practice, everything ends up as an inout, and you may or may not get a warning. So, you can do pretty much anything in a simulator, but a linter or a synthesiser should pick up any logical connection errors for you (if it doesn't, it's pretty useless). There are other specific non-direction rules in the following sections - input and inout ports have to be of net type, and so on.
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