Simulink中并行到串行块的问题 [英] Problem with Parallel-to-Serial block in Simulink

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问题描述

我正在尝试将DQPSK解调器(类型:UFix2_0)发出的输入字转换为串行流.

I am trying to convert the input word coming out of the DQPSK Demodulator (Type : UFix2_0) to a serial stream.

所以我正在Simulink中使用Xilinx库的并行到串行块.

So I am using the Parallel-to-Serial Block of Xilinx Library in Simulink.

但是我无法使用该块,出现以下错误:

But I am not able to use the block, I get the following error :

"Simulink系统周期"设置 在此系统生成器令牌上不是 适用于 设计.

"The Simulink system period" setting on this System Generator token is not appropriate for the rates used in the design.

当前设置为:1 An 适当的设置是:1/2"

The current setting is: 1 An appropriate setting is: 1/2 "

我也尝试更改系统生成器的设置,但是它似乎也不起作用.

I tried to change the setting the System Generator as well, but It does not seem to work as well.

任何想法,我可能会出错.任何其他方法也将有所帮助.

Any idea where I might be going wrong. Any other approach would be helpful as well.

谢谢

推荐答案

在Xilinx Sysgen文档中搜索"simulink系统周期"

Search for "simulink system period" in the Xilinx Sysgen documentation

  1. http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/sysgen_gs.pdf
  2. http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/sysgen_user.pdf
  3. http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/sysgen_ref.pdf
  1. http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/sysgen_gs.pdf
  2. http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/sysgen_user.pdf
  3. http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/sysgen_ref.pdf

入门指南(1)显示了如何在具有多种速率的系统中计算simulink系统周期(您可以使用并行串行模块获得该速率).基本上,simulink系统周期是模型中出现的采样周期的最大公分母.似乎在系统周期的设置方式与速率更改块前后(与串行)平行的周期之间存在冲突.

The getting started guide (1) shows how to calculate the simulink system periods in a system with multiple rates (which you get by using the parallel to serial block). Basically the simulink system period is the greatest common denominator of the sample periods that appear in the model. It looks like you have a conflict between how the system period is set and the periods before and after your rate changing block (parallel to serial).

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