x86-64:缓存加载和逐出指令 [英] x86-64: Cache load and eviction instruction

问题描述

对于x86-64体系结构，是否有一条指令可以将给定内存地址的数据加载到缓存?同样，是否有一条指令可以在给定与该缓存行相对应的内存地址(或类似缓存行标识符的内存地址)的情况下逐出缓存行?

For x86-64 architecture, is there an instruction that can load data at a given memory address to the cache? Similarly, is there an instruction that can evict a cache line given a memory address corresponding to that cache line (or something like a cache line identifier)?

推荐答案

将数据预取到缓存中(不将其加载到寄存器中):

prefetch data into cache (without loading it into a register):

PREFETCHT0 [address]
PREFETCHT1 [address]
PREFETCHT2 [address]

本征:void _mm_prefetch (char const* p, int hint)

请参见 insn ref手册和其他指南，了解不同的邻近提示的含义. ( x86 标签wiki的问题.)

See the insn ref manual and other guides for what the different nearness hints mean. (Other links at the x86 tag wiki).

着名的在P4编写时，每个程序员都应该知道的内容当前的.当前的CPU具有更智能的硬件预取器，而超线程的作用不仅限于运行预取线程. AFAIK，预取线程通常是一个绝妙的主意.除此之外，关于缓存的出色文章.搜索其他SO帖子和内容，以决定何时实际进行预取.

The famous What Every Programmer Should Know About Memory article was written when P4 was current. Current CPUs have smarter hardware prefetchers, and hyperthreading is useful for much more than just running prefetch threads. AFAIK, prefetch threads are mostly a dead idea. Other than that, excellent article about caching. Search for other SO posts and stuff to decide when to actually prefetch.

不要不要用Intel IvyBridge上的软件预取功能过度覆盖它.该特定的微体系结构存在性能错误，只能退休每43个时钟一次预取.

Do not overdo it with software prefetch on Intel IvyBridge. That specific microarchitecture has a performance bug, and can only retire one prefetch per 43 clocks.

刷新包含给定地址的缓存行:

Flush the cache line containing a given address:

clflush [address]
clflushopt [address]   ; Newer CPUs only.  Weakly ordered, with higher throughput.

本征:void _mm_clflushopt (void const * p)

有一个最近关于其性能的问题.

这篇关于x86-64:缓存加载和逐出指令的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！