在 x86-64 上，是“movnti"指令原子? [英] On x86-64, is the "movnti" instruction atomic?

问题描述

在 x86-64 CPU(Intel 或 AMD)上，将 4/8 字节写入 32/64 位对齐地址的movnti"指令是原子的吗?

On x86-64 CPUs (either Intel or AMD), is the "movnti" instruction that writes 4/8 bytes to a 32/64-bit aligned address atomic?

推荐答案

是的，movnti 在自然对齐的地址上是原子的，就像所有其他自然对齐的 8/16/32/64b 在 x86 上存储(和加载)一样.这适用于任何内存类型(回写、写组合、不可缓存等).请参阅该链接以了解英特尔 x86 手册中的保证措辞.

Yes, movnti is atomic on naturally-aligned addresses, just like all other naturally-aligned 8/16/32/64b stores (and loads) on x86. This applies regardless of memory-type (writeback, write-combining, uncacheable, etc.) See that link for the wording of the guarantees in Intel's x86 manual.

请注意，原子性与内存排序是分开的.正常的 x86 存储是 release-store 操作，但 movnt 存储是放松的".

Note that atomicity is separate from memory ordering. Normal x86 stores are release-store operations, but movnt stores are "relaxed".

趣闻:32 位代码可以使用 x87 (fild/fistp) 或 SSE/MMX movq 来做原子 64 位加载/存储.gcc 的 std::atomic 实现实际上就是这样做的.只有大于 8B 的 SSE 访问(例如 movaps 或 movntps 16B/32B/64B 向量存储)不能保证原子性.(即使 16B 操作在某些硬件上也是原子操作，但没有标准方法可以检测到这一点).

Fun fact: 32-bit code can use x87 (fild/fistp) or SSE/MMX movq to do atomic 64-bit loads/stores. gcc's std::atomic implementation actually does this. It's only SSE accesses larger than 8B (e.g. movaps or movntps 16B/32B/64B vector stores) that are not guaranteed atomic. (Even 16B operations are atomic are on some hardware, but there's no standard way to detect this).

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