奇异硬件上的C ++ 11 [英] C++11 on exotic hardware
问题描述
2011年以前曾有这样一个问题： Exotic体系结构标准委员会在意
There was a question like this before, in 2011: Exotic architectures the standards committees care about
现在，我想问一个非常相似的问题，但是这次，我是从程序员的角度出发，并且从C ++ 11的角度来看。
Now, I'd like to ask a very similar question, but this time, I'm asking it from the programmer's view of perspective, and in the perspective of C++11.
当前存在哪些硬件，该硬件具有C ++ 11编译器，可以被认为是奇特的？
Which hardwares exist currently, which has a C++11 compiler for it, and can be considered exotic?
我认为异国情调是什么？
What do I consider exotic?
- 其中的字符不是8位
- 其中IEEE 754浮点数格式不可用
- 其中整数不以两个补码编码
- 编译器不支持8、16或32位类型
- 内存模型不是线性的（因此，您不能比较/减去任何指针） $ b
所以不是标准的任何东西，我们在x86 / ARM世界中看到的是：
So anything, which is not the standard, which we see on x86/ARM world, where we have:
- 具有8/16/32位的两个补码整数
- IEEE754浮点型，有些完全兼容，有些不兼容，但使用IEEE754格式
- 线性内存模型
注意：我想提供答案，其中存在与C ++ 11兼容的编译器，而不是存在C ++编译器的硬件，但是没有
Note: I'd like to have answers, where a C++11 conformant compiler exists for the hardware, not where a C++ compiler exists, but isn't fully conformant.
我问这是因为，很多时候，我会得到诸如您不能依赖它，它是实现定义的之类的答案，并且我想知道，实际上，在现实世界中，我可以依靠 standard 多少钱。只是一个例子：每当我写 std :: uint16_t 时，我可能会担心（由于此功能是可选），在平台上，这种类型不存在。但是，有没有一个不存在这种类型的实际平台？
I'm asking this, because a lot of times, I get answers like "you cannot depend on that, it is implementation defined", and I'd like to know, that actually, in the real world, how much I can depend on the standard. Just an example: whenever I write std::uint16_t, I may worry (as this feature is optional), that on a platform, this type is non-existent. But, is there an actual platform, where this type doesn't exist?
推荐答案
去寻找DSP内核，那是您最好的选择
Go looking for DSP cores, that's your best bet for "exotic" architectures.
例如，Motorola / Freescale / NXP 56720具有Tasking可用的C ++编译器，但在三个或三个以上具有24位内存公共汽车。我认为设备（至少是较旧的56K设备）上的堆栈模型是硬件堆栈，并不真正适合C / C ++模型。
For example, the Motorola/Freescale/NXP 56720 has a C++ compiler available from Tasking, but has 24-bit memory on three or more buses. I think the stack model on the device (at least the older 56K devices) was a hardware stack and didn't really fit the C/C++ model.
编辑：更多详细信息...
edit: more details...
该野兽的寄存器模型很奇怪：
The register model on this beast is odd:
- 累加器（56位，分为8位，24位，24位子寄存器）
- 数据寄存器（24或48位）
- 地址寄存器（R0..7，M0..7和N0..7）用于地址，模和步长
模和步长寄存器不会映射到C / C ++内在建模的任何内容，因此总是有一些奇数球构造和 #pragma 来帮助编译器支持循环缓冲区
The modulo and step size registers don't map to anything intrinsically modeled in C/C++, so there's always some oddball constructs and #pragma to help the compiler along to support circular buffers.
没有堆栈指针（没有push或pop指令）。有一个用于函数返回地址的硬件堆栈，但是深度只有16个调用。该软件必须管理溢出并且局部变量不能存在于堆栈中。
There's no stack pointer (no push or pop instruction). There's a hardware stack for function return addresses, but that's only 16 calls deep. The software has to manage overflows and local variables don't live in on the stack.
由于没有堆栈，因此编译器会执行诸如静态调用树分析之类的怪异操作，并放置覆盖的内存池中的局部变量。这意味着没有重入功能，并且必然只有一个上下文而没有太多怪异或严重的性能损失。
Because there's no stack, the compiler does weird things like static call tree analysis and puts local variables in overlayed memory pools. This means no re-entrant functions and necessarily only one context without much weirdness or severe performance penalties.
sizeof（int） = sizeof（char） = sizeof（short） = 1 = 24位
sizeof(int) = sizeof(char) = sizeof(short) = 1 = 24 bits
这意味着没有字节访问权限（至少在旧的56002上，不确定56300）。我认为从24位整数数组中读取/写入特定字节大约需要24个周期。这个内核不好，并且桶形移位，掩蔽和或运算。
This means no byte access (at least on the old 56002, not sure about the 56300). I think it takes about 24 cycles to read/write a specific byte from an array of 24-bit integers. This core is not good and barrel shifting, masking, and or-ing
当然，并非所有DSP内核都像这样，但是它们通常具有不同程度的怪异从32/64位统一内存的标准和GCC的sizeof（char）= 1期望值开始，这是因为固有的模指针和多个内存总线。
Not ALL DSP cores are like this of course, but they're usually varying degrees of 'weird' from the standard of 32/64 bit unified memory and sizeof(char)=1 expectations of GCC because of the intrinsic modulo pointers and multiple memory buses.
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