ARM 上的硬件断点 [英] Hardware breakpoints on ARM

问题描述

硬件断点如何在 ARM 处理器上工作?我可以看到在 x86 和 x64 上有 6 个调试寄存器，从 DR0 到 DR7.有人可以向我指出资源与此类似但适用于 ARM 吗?

How do hardware breakpoints work on ARM processors? I can see that on x86 and x64 there are 6 DEBUG registers, DR0 throught DR7. Can someone point me to resources similar to this but for ARM?

推荐答案

ARM 架构支持硬件和软件断点.在 Cortex A7(来自 ARM 的 ARM v7a 实现)中有六个硬件断点可用.结帐部分:的10.2.2(断点和观察点)Cortext A7 TRM

ARM architectures support both Hardware and Software breakpoints. In Cortex A7 (an ARM v7a implementation from ARM) six hardware breakpoints are available. Checkout section: 10.2.2 (Breakpoints and Watchpoints) of the Cortext A7 TRM

当您用完硬件断点时，调试器会插入一条 BKPT 指令以停止执行.

When you run out of hardware breakpoints, there is a BKPT instruction which the debugger inserts to halt execution.

您必须参考您正在查看的特定芯片的技术参考手册 (TRM)，了解硬件断点的确切数量.

You will have to refer to the Technical Reference Manual (TRM) of the particular chip you are looking at for the exact number of hardware breakpoints.

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