ARM的硬件断点 [英] Hardware breakpoints on ARM

问题描述

如何硬件断点在ARM处理器上运行？我可以看到，在x86和x64有6个调试寄存器，DR0 throught DR7。有人能指出我的资源与此类似但对于ARM？

How do hardware breakpoints work on ARM processors? I can see that on x86 and x64 there are 6 DEBUG registers, DR0 throught DR7. Can someone point me to resources similar to this but for ARM?

推荐答案

ARM体系结构支持硬件和软件断点。在皮质A7（从ARM的ARM V7A实现）六硬件断点可用。 Checkout部分：10.2.2（断点和观察点）的<一个href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464d/DDI0464D_cortex_a7_mpcore_r0p3_trm.pdf\"相对=nofollow> Cortext A7 TRM

ARM architectures support both Hardware and Software breakpoints. In Cortex A7 (an ARM v7a implementation from ARM) six hardware breakpoints are available. Checkout section: 10.2.2 (Breakpoints and Watchpoints) of the Cortext A7 TRM

当您运行的硬件断点，有一个BKPT指令，调试器插入停止执行。

When you run out of hardware breakpoints, there is a BKPT instruction which the debugger inserts to halt execution.

您将要参考的技术参考你正在寻找的硬件断点的确切数目的特定芯片手册（TRM）

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