如何精确计算直接映射缓存的命中率? [英] How exactly to count the hit rate of a direct mapped cache?
问题描述
我们获得了一个包含8帧的缓存,并且将其直接映射。已观察到对主存储块的以下访问顺序:
2 5 0 13 2 5 10 8 0 4 5 2
计算此组织缓存的命中率。
解决方案:
我知道数字的放置方式和原因。但是我不明白为什么2和5会被加粗,为什么我们的命中率达到17%。
这已经由我们的教授解决了,但是我不知道
就像@Margaret Bloom在评论中提到的那样,粗体数字指的是cache-命中。非粗体表示缓存未命中。
使用此模拟器可能会更好地理解它:
We got a cache given with 8 frames and it's directly mapped. Following access sequence on main memory blocks has been observed:
2 5 0 13 2 5 10 8 0 4 5 2
Count the hit rate of this organized cache.
Solution:
I understand how and why the numbers are placed in the table like that. But I don't understand why 2 and 5 have been bold-printed and why we got hit rate of 17%.
This has been solved by our professor but I don't understand it completely.
Like was mentioned by @Margaret Bloom in the comments, the numbers in bold refer to cache-hits. Non-bold refer to cache misses.
You might understand it better by using this simulator: cachesimulator.com
The Simulator works with WORD-instructions only, so a little conversion of your assignment need to be made in order to simulate it:
cache-size: 32 bytes (8 rows)
block-size: 4 bytes (one word per row)
associativity: 1 (direct-mapped cache)
replacement algorithm: LRU
memory size: (any number larger than (14*4) works) for example: 1024
Now since the simulator works with WORD-instructions you need to convert your access sequence by multiplying each number by 4, also, in the simulator you enter addresses in hexadecimal so after you have multiplied by 4 you convert to hexadecimal, then you get:
8 14 0 34 8 14 28 20 0 10 14 8
In the simulator you enter instructions on the form:
<operationtype><space><register><space><address>
In your case the operationtype is LOAD and the register does'nt matter. So you can use any register, for example:
LOAD 1 8
LOAD 1 14
LOAD 1 0
LOAD 1 34
LOAD 1 8
LOAD 1 14
LOAD 1 28
LOAD 1 20
LOAD 1 0
LOAD 1 10
LOAD 1 14
LOAD 1 8
Enter the instructions above in the text-area of the simulator and click run. You can then see the cache hits and misses in real-time and when the simulation is finnished you can analyze the results by looking at the content of the cache memory and the list of instruction-results. You can view the main-memory address that each element in the cache refers to by hovering over it.
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