缓存未命中如何发生？ [英] How does a cache miss EXACTLY occur?

问题描述

我正试图了解缓存未命中的确切原因。到目前为止，这就是我的理解方式：

CPU请求地址x，并在其自己的（L1 / L2）缓存中搜索。如果不存在，则可能是缓存未命中。

现在，这里缺少的是如何准确地找到缓存中不可用的信息？缓存行保留哪些信息？到目前为止，我知道缓存行应包含以下信息：

I'm trying to understand how exactly a cache miss occurs. So far this is the way I understand it:
CPU requests for address x, searches its own (L1/L2) cache for it. If it is not there then it's a cache miss.
Now what is missing here is how exactly does it find out that the information is not available in cache? What information do cache lines reserve? So far I know a cache line should contain this information:

Address of the information, Data within that address.  

具有此信息，CPU可以找出其缓存中是否有地址可用。当它具有无效的数据副本时，就会出现问题。所以我的问题是：

处理器如何找出某些数据有效还是无效？

每条高速缓存行中是否存储有标志？是否要求协议提供此信息？如果是这样，协议的信息保存在哪里（缓存/内存/其他地方）？

我仍​​在搜索，但是我很乐意为此提供任何资源。

Having this information CPU can find out whether an address is available in its cache or not. The problem arises when, it has an invalid copy of data. So my question would be:
How does the processor find out if some data is valid or invalid?
Are there flags stored in each cache line? Does it ask the protocol for this information? If so, where are protocol's information kept(Cache/Memory/Elsewhere)?
I'm still searching, but I'd appreciate any resources on this.

-编辑

问类似的问题此处，但没有答案。似乎没有MESI协议的详细信息。任何帮助表示赞赏。

--EDIT
Similar question asked here, yet no answer. There doesn't seem to be any detailed information of MESI protocol. Any help is appreciated.

-EDIT2

我在 MESI CMP目录。它指出 L2高速缓存控制器片上目录与L2高速缓存中的相应高速缓存块位于同一位置，但是关于L1高速缓存控制器信息所处的位置无关。

--EDIT2
I found more info in MESI CMP Directory. It states that "L2 cache controller on-chip directory is co-located with the corresponding cache blocks in L2 Cache", but nothing about where L1 cache controller information resides.

推荐答案

缓存行（L1或L2）包含以下信息：

The cache line (L1 or L2) contains the following information:

dirty_bit | many_memory_word

当脏位包含1时，表示行缓存不存在类似于RAM中的通讯员。当它包含0时，这意味着行高速缓存实际上在RAM中包含该存储器行的确切副本。

When the dirty bit contains 1 that means the line cache is not similar to the correspondent in the RAM. When it contains 0 that means the line cache contains the exact copy of the memory line actually in the RAM.

当CPU请求RAM中的地址时，将进行转换使用MTL具有相应的行缓存地址，该地址应该包含该信息。

When the CPU request an address in the RAM, a translation is made using the MTL to have a correspondent line cache address which is supposed to contain the information.

如果未找到地址，则表示信息不在高速缓存行上，然后发生高速缓存未命中。如果找到了缓存中的地址，则如果将缓存中请求的行的脏位设置为1，则会发生缓存未命中，并且将实际写入行缓存中的信息回到内存中。缓存中的行地址使CPU知道真实内存RAM中对应的地址。

If there is no address found, that means the information is not on the cache line and then a cache miss happens. If an address on the cache is found, then if the dirty bit of the line requested in the cache is set to 1, a cache miss will happen, and the information actually in the line cache will be written back in memory. The address of the line in the cache makes the CPU know which address corresponds in the real memory RAM.

因此，当CPU从内存中请求信息时，该信息（以及（更多）放在行缓存中，并且脏位设置为0，这意味着缓存行表示RAM中内存行的确切副本。

So when the CPU requesst an information from memory, this information (and more) are put on the line cache, and the dirty bit is set to 0 that means that the cache line represents the exact copy of memory line in the RAM.

然后，当在行缓存中进行写操作时，CPU将脏位设置为1，这意味着该行不再代表复制实际上存在于RAM中。因此，如果对脏位设置为1的缓存中的地址进行读取操作，则会发生缓存未命中。

Then, when writing operations occur in the line cache, the CPU sets the dirty bit to 1 that means the line does no longer represent the copy actually present in the RAM. So if a reading operation occurs on an address in the cache whose dirty bit is set to 1, a cache miss happens.

参考：请在此处进行了解。

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