包容性还是排他性？ Intel Core IvyBridge处理器中的L1，L2缓存 [英] Inclusive or exclusive ? L1, L2 cache in Intel Core IvyBridge processor

问题描述

我有3.40GHz（L1-32KB，L2-256KB，L3-8MB）的Intel Core IvyBridge处理器，Core Core i7-3770 CPU。我知道L3是包容性的，并且在多个内核之间共享。我想了解有关我的系统的以下信息

I am having Intel Core IvyBridge processor , Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz( L1-32KB,L2-256KB,L3-8MB). I know L3 is inclusive and shared among multiple core. I want to know the following with respect to my system

PART1：

1. L1是包含性还是排他性？


2. L2是包含性或排他性吗？

PART2：

如果L1和L2都包含两个端点，那么为了找到L2的访问时间，我们首先声明一个数组（1MB）大于L2缓存（256KB）的大小，然后开始访问整个阵列以加载到L2缓存中。此后，我们以64B的步长从开始索引到结束索引访问数组元素，因为缓存行大小为64B。为了获得更好的准确结果，我们重复此过程（访问索引处，起始端处的数组元素）多次，比如说进行一百万次并取平均值。

If L1 and L2 are both inclusive then to find the access time of L2 we first declare an array(1MB) of size more than L2 cache(256KB) , then start accessing the whole array to load into L2 cache. After that we access the array element from start index to end index with stride of 64B as cache line size is 64B. To get better accurate result we repeat this process(accessing array elements at index ,start-end) for multiple times, say 1 million times and takes the average.

我的理解为什么这种方法会给出正确的结果，如下所示：
当我们访问大小大于L2缓存大小的数组时，整个数组将从主内存加载到L3，然后从L3加载到L2，再从L2加载到L1。整个数组的最后32KB在L1中，因为它最近被访问过。由于具有包容性和缓存一致性，整个阵列也存在于L2和L3缓存中。现在，当我从起始索引再次开始访问数组时，该索引在L1高速缓存中不是不是，而是在L2高速缓存中，因此将出现高速缓存未命中，并且将从L2高速缓存中加载它。这样，整个数组的所有元素将需要更长的访问时间，总的来说，我将获得整个数组的总访问时间。要获得单次访问权限，我将获得总访问次数的平均值。

My understanding why this approach gives correct result as follows- When we access the array of size more than L2 cache size, then whole array is loaded from main memory to L3, then from L3 to L2, then L2 to L1. The last 32KB of the whole array is in L1 as it is recently accessed. The whole array is also present in L2 and L3 cache also due to inclusive property and cache coherency . Now, when I start accessing the array again from starting index, which is not in L1 cache, but in L2 cache, so there will be a cache miss and it will be loaded from L2 cache. And this way there will be higher access time required for all elements of whole array and in total I will get the total access time of whole array. To get the single access I will take the average of total no of access .

我的问题是-我正确吗？

谢谢。

推荐答案

请参阅《英特尔优化指南》中的2.2.5节-

http：// www。 intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf

See section 2.2.5 in the Intel optimization guide -
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf

（请注意，这适用于Sandy-Bridge，但似乎不适用于Ivy-Bridge，因为Ivy-Bridge与上一代产品相比只有很小的微体系结构更改。）

(note that this applies for Sandy-Bridge, but doesn't appear as changed for Ivy-Bridge, which has only minor micro-architectural changes over the previous generation).

所以关于您的问题：

1. 对于L1来说，没有包容性的问题，因为它没有上层缓存-of


2. L2缓存不包含，这意味着不能保证驻留在L1中的行也必须位于L2中​​。但是，在大多数情况下，它很可能存在，因为它可能是在最初由核心请求时填充到L2中的，并且有很大的机会在L2中生存更长的时间，因为它更大（因此驱逐）最好分布在更多集合上），并按L1过滤（通常意味着更少的逐出）

1. For the L1 there's no question of inclusiveness as it doesn't have upper level caches to be inclusive-of
2. The L2 cache is not inclusive, meaning that there's no guarantee that a line residing in the L1 would have to be in the L2 as well. However on most cases it's likely to be there since it was probably filled into the L2 when originally requested by the core, and has a good chance to survive longer in the L2 since it's bigger (and therefore the evictions are better spread over more sets), and filtered by the L1 (meaning less evictions usually)

还请注意，如果您的基准测试正在访问一个大于L2的数据集，它可能无法放置在L2中（特别是如果您串行访问它并且超出L2的大小超过单一方式的大小），则必须从L2中获取它。 L3。

Also note that if your benchmark is accessing a data-set larger than the L2, it will probably fail to sit in the L2 (especially if you access it serially and exceed the L2 by more than the size of a single way), and you'd have to fetch it from the L3.

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