Core i7中每核L2和L3之间的互连 [英] Interconnect between per-core L2 and L3 in Core i7

问题描述

英特尔酷睿i7具有每核L1和L2缓存，以及大型共享的L3缓存。我需要知道哪种互连将多个L2连接到单个L3。我是一名学生，需要编写缓存子系统的粗略行为模型。
它是横线吗？一辆公共汽车？戒指？我遇到的参考文献都提到了缓存的结构细节，但是都没有提及存在哪种片上互连。

The Intel core i7 has per-core L1 and L2 caches, and a large shared L3 cache. I need to know what kind of an interconnect connects the multiple L2s to the single L3. I am a student, and need to write a rough behavioral model of the cache subsystem. Is it a crossbar? A single bus? a ring? The references I came across mention structural details of the caches, but none of them mention what kind of on-chip interconnect exists.

谢谢，

-neha

推荐答案

现代i7使用环。从汤姆的硬件：

今年早些时候，我有幸与Intel的
高级工程师Sailesh Kottapalli进行了交谈，他解释说， d从Xeon 7500系列的LLC看到
的持续带宽接近300 GB / s，环形总线启用了
。此外，英特尔在IDF上确认，目前正在开发的每款产品
都使用环形
总线。

Earlier this year, I had the chance to talk to Sailesh Kottapalli, a senior principle engineer at Intel, who explained that he’d seen sustained bandwidth close to 300 GB/s from the Xeon 7500-series’ LLC, enabled by the ring bus. Additionally, Intel confirmed at IDF that every one of its products currently in development employs the ring bus.

您的模型将非常粗糙，但是您可以从有关L3的i7性能计数器的公共信息中收集更多信息。

Your model will be very rough, but you may be able to glean more information from public information on i7 performance counters pertaining to the L3.

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