数据总线宽度和字长 [英] Data bus width and word size

问题描述

当字长改变时，数据总线宽度会改变吗？

Will data bus width size change when word size changes?

我认为它将改变，因为数据总线宽度通常是字长的倍数。因此，如果字长改变了，数据总线的宽度也会改变。

I think that it will change because data bus width is usually in multiples of word size. So if word size changes, data bus width also changes.

我正确吗？

推荐答案

是的，如果您制作了x86的变体，具有9位字节/ 36位 dword，则其内部和外部总线将是该倍数，而不是64位的倍数。

Yes, if you made a variant of x86 with 9-bit bytes / 36-bit "dword", then its internal and external busses would be multiples of that instead of multiples of 64 bits.

但除此之外，字长与内部/外部总线宽度之间的比率是灵活的。您可以通过加宽各种总线或增加字长（或非整数寄存器的寄存器宽度）来改变该比率。

But otherwise no, the ratios between word size and internal / external bus widths are flexible. You can let that ratio change as you widen various buses or increase the "word size" (or register width for non-integer registers).

x86（自P5以来）奔腾在架构上要求具有原子的64位
加载/存储以对齐的指针。到目前为止，实现此功能最简单的方法是使用64位/ 128位/ 256位/ 512位数据公共汽车。英特尔之所以能够在P5中免费提供原子性保证，是因为它们将其内部和外部数据总线扩展到了64位。因此，即使对于那一代的 32位 x86 CPU，如果要与奔腾兼容，也不能选择32位总线。

x86 since P5 Pentium is architecturally required have atomic 64-bit loads/stores for aligned pointers. By far the easiest way to implement this is with 64-bit / 128-bit / 256-bit / 512-bit data busses. Intel was able to make that atomicity guarantee basically for free in P5 because they widened its external and internal data busses to 64-bit. So even for "32-bit" x86 CPUs of that generation, 32-bit busses weren't an option if they wanted to be compatible with Pentium.

现代x86 CPU具有最多512位（64字节）宽的内部数据路径。例如Skylake在L2和L1缓存之间具有64字节宽的路径。 Skylake-AVX512具有64字节的加载/存储单元。即它可以一次加载/存储整个缓存行。 （外部数据总线是64位DDR3 / 4 DRAM，可对整个64字节高速缓存行进行突发传输。当然，对于非DRAM访问，传输通过PCIe进行。）

Modern x86 CPUs have internal data paths up to 512 bits (64-bytes) wide. e.g. Skylake has a 64-byte wide path between L2 and L1 cache. Skylake-AVX512 has 64-byte load/store units. i.e. it can load/store whole cache lines at once. (The external data bus is 64-bit DDR3/4 DRAM that does burst transfers of whole 64-byte cache lines. Of course, for non-DRAM access, transfers go over PCIe)

Sandybridge / Ivybridge做AVX 256位加载/存储为两个128位（16字节）的一半，因为从执行单元到L1D的数据路径只有一半与寄存器大小一样宽。请参见如何快速进行缓存？

Sandybridge / Ivybridge do AVX 256-bit loads/stores as two 128-bit (16-byte) halves, because the data path from execution units to L1D are only half as wide as the register size. See How can cache be that fast?

AMD Bulldozer系列和Ryzen将所有256位运算拆分为128位，所以实际上是将两个单独的负载分成两个单独的向量寄存器，它们被视为一个体系结构YMM寄存器。这与SnB / IvB不同，在其中 vaddps ymm 是单个uop，只是加载/存储在加载/存储执行单元中需要两个周期，因为总线不是

AMD Bulldozer-family and Ryzen split all 256-bit ops into 128-bit halves, so it's really two separate loads into two separate vector registers which get treated as one architectural YMM register. This is different from SnB/IvB where vaddps ymm is a single uop, it's just that loads/stores need two cycles in the load/store execution unit because the bus isn't as wide as the physical registers.

使用不同的FPU和SIMD寄存器宽度，整数寄存器宽度和字长不再像以前那样有意义！同样的概念适用，但是重要的是寄存器宽度而不是字长。

With different FPU and SIMD register widths, the integer register width and "word size" are not as meaningful as they used to be! The same concepts apply, but it's just register width not "word size" that matters.

这篇关于数据总线宽度和字长的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！