ARM LL/SC 通过寄存器宽度或缓存线宽度进行独占访问? [英] ARM LL/SC exclusive access by register width or cache line width?

问题描述

我正在开发下一个版本的无锁数据结构库，在 ARM 上使用 LL/SC.

I'm working on the next release of my lock-free data structure library, using LL/SC on ARM.

对于我的 LL/SC 用例，我需要将它与 LDREX 和 STREX 之间的单个 STR 一起使用.(而不是用它来模拟 CAS.)

For my use-case of LL/SC, I need to use it with a single STR between the LDREX and STREX. (Rather than using it to emulate CAS.)

现在，我已经编写了代码，并且可以正常工作.然而，我担心的是它可能并不总是有效.我在 PowerPC 上读过，如果您访问与 LL/SC 目标相同的缓存行，就会破坏 LL/SC.

Now, I've written the code and this works. What concerns me however is the possibility it may not always work. I've read on PowerPC if you access the same cache line as the LL/SC target, you break the LL/SC.

所以我在想，如果我的 STR 目标与我的 LL/SC 目标在同一缓存行上，那么 pow，我死了.

So I'm thinking if my STR target is on the same cache line as my LL/SC target, then pow, I'm dead.

现在，LL/SC 目标和 STR 目标始终位于不同的 malloc() 中，因此它们直接位于同一缓存行中的机会可能很小(我可以通过填充 LL/SC 目标来保证这一点，所以它从缓存线边界开始并填充该缓存线).

Now, the LL/SC target and STR targets are always in different malloc()s so the chance of them being directly in the same cache line is probably small (and I can guarantee this by padding the LL/SC target so it begins on a cache line boundary and fills that cache line).

但如果 STR 目标在内存中的正确(错误！)位置，则可能存在错误共享.

But there could be false sharing, if the STR target is in just the right (wrong!) place in memory.

查看 LDREX/STREX 文档，这描述了物理地址"方面的独占访问.这意味着寄存器宽度粒度，而不是缓存行宽度粒度.

Looking at the LDREX/STREX documentation, this describes exclusive access in terms of "the physical address". This implies register width granularity, not cache line width granularity.

这是我的问题 - LDREX/STREX 是否对使用寄存器宽度粒度或缓存线宽度粒度的内存访问敏感?

And that's my question - is LDREX/STREX sensitivity to memory access using register width granularity or cache line width granularity?

推荐答案

ARM 使用 Exclusive Monitors 通过 load-linked/store-conditional 实现对内存的独占访问.[1] 包含所有细节，这里我想说的是:

ARM uses Exclusive Monitors to implement exclusive access to memory via load-linked/store-conditional. [1] has all the details, of importance here I'd say is the following:

独家预订颗粒

当独占监视器标记地址时，可以被标记为独占访问称为独占预订颗粒(ERG).ERG 是在 8-2048 范围内定义的实现字节，以两个字节的倍数表示.可移植代码不能假设任何关于 ERG 大小的信息.

When an exclusive monitor tags an address, the minimum region that can be tagged for exclusive access is called the Exclusives Reservation Granule (ERG). The ERG is implementation defined, in the range 8-2048 bytes, in multiples of two bytes. Portable code must not assume anything about ERG size.

所以在我看来，你有点不走运.无论如何，大多数实际实现可能会保持一个很小的值，但据我所知，基本的 ARM 架构并不能保证，但也许有更多经验的人会发现我错了.:)尽管如此，LL/SC 的所有实现都是某种形式的弱 LL/SC，所以你几乎永远不能完全确定 LL 和 SC 之间的存储不会总是杀死 SC，或者大多数时间，或者可能永远不会......它只是依赖于架构和实现，我个人坚持使用 LL/SC 在紧密循环中实现 CAS，并像往常一样使用它并完成它.

So you're kinda out of luck there as I see it. Most real implementations will probably keep a small value anyway, but it's not guaranteed by the basic ARM architecture as far as I can tell, but maybe someone with more experience will find me wrong. :) Still, kinda all implementations out there of LL/SC are some form of weak-LL/SC, so you can almost never be completely sure that a store between the LL and the SC won't kill the SC always, or most of the time, or maybe never... It's just so much architecture and implementation dependent that I personally stick to using LL/SC to implement CAS in a tight loop and use that as usual and be done with it.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGCFAF.html

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