Intel Xeon Broadwell双处理器之后会怎样？ [英] What comes after Intel Xeon Broadwell dual processors?

问题描述

我正在编译数据以比较CPU和GPU GFLOP性能，并且我目前正在研究双插槽CPU（E5-26xx系列），但是在Broadwell推出具有Bronze和Silver双处理器系列的Skylake架构之后，具有比Broadwell核心和性能一半的核心和性能。我错过了什么吗？

I'm compiling data to compare CPU and GPU GFLOP performance, and I'm looking currently at dual socket CPUs (E5-26xx family), however after Broadwell comes Skylake architecture which has Bronze and Silver dual processor families, but they have half the cores and performance than the Broadwell ones. Am I missing something?

推荐答案

有趣的是，似乎您是对的，只有高核数的Skylake服务器芯片也可以用于四路系统。 （ https://en.wikichip.org/wiki/intel/ microarchitectures / skylake_（server）#Brands ）

Interesting, it seems you're right that the only high-core-count Skylake-server chips are also capable of being used in 4-socket systems. (https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#Brands)

您可以将Gold / Platinum CPU放入双插槽系统。我假设您在高核数CPU中要支付的大部分钱是内核/缓存本身，因此在2插槽系统中使用它们并不是浪费。

You can put Gold / Platinum CPUs in dual-socket systems. I assume most of what you're paying for in the high-core-count CPUs is the cores / cache themselves, so it's not a waste to use them in a 2-socket system.

SKX使用UPI而不是QPI作为套接字之间的互连。具有2个UPI链接的CPU可以在4P系统中使用，而不是每个CPU中具有3个链接的全部到全部形成一个环。或者2P系统可以使用两个插槽之间的所有3个UPI链接以获得更大的带宽。 （ Wikichip有图）

SKX uses UPI instead of QPI as the interconnect between sockets. A CPU with 2 UPI links can be used in a 4P system, forming a ring instead of an all-to-all with 3 links in each CPU. Or a 2P system can use all 3 UPI links between the two sockets for more bandwidth. (Wikichip has diagrams)

铜/银和金5xxx CPU具有2个UPI链接，而金6xxx和铂金CPU具有3个UPI链接。 （维基百科）

Bronze / Silver, and Gold 5xxx CPUs have 2 UPI links, while Gold 6xxx and Platinum CPUs have 3 UPI links. (wikipedia)

在每个Skylake-SP CPU内部（在单个裸片上），内核之间的互连是网状的，而Broadwell和更早版本中的环形总线则是环形的。

Inside each Skylake-SP CPU (on a single die) the interconnect between cores is a mesh, vs. a ring bus in Broadwell and earlier.

4P / 8P Broadwell（或更早的版本）Xeon的侦听过滤器缓存很小（14kiB？我现在找不到更详细的描述）（请参阅 John McCalpin在此线程中的帖子，但使用2P芯片不会，只是在L3中的负载丢失时，将侦听请求广播到从本地DRAM加载的其他套接字。这占用了QPI带宽的一部分。（确切的侦听行为是可配置为不同模式以便针对低延迟本地内存进行优化，而针对远程内存则可以减少较差的延迟，依此类推）。

4P/8P Broadwell (and earlier) Xeons have a small (14kiB? I can't find a more detailed description right now) snoop filter cache (see John McCalpin's post in this thread, but 2P chips don't, and just broadcast snoop requests to the other socket as they load from local DRAM, when a load misses in L3. This "uses a modest fraction of the QPI bandwidth". (The exact snoop behaviour is configurable with different modes to optimize for low-latency local memory vs. less-bad latency for remote memory, and so on).

因此，存在一种硬件（不仅仅是人工营销/市场） -segmentation）在Broadwell和更早版本中具有相同内核数的2P和4P / 8P芯片之间的差异。

Thus there is a hardware (not just artificial marketing / market-segmentation) difference between 2P and 4P/8P chips with the same core count for Broadwell and earlier.

Skylake-SP总是有一个监听过滤器。请参阅部分

Skylake-SP always has a snoop filter. See the Directory-Based Coherency section in Intel's paper on Skylake-Xeon internals.

（IDK详细信息。也许铜/银芯片较弱，但他们的市场部门决定在金牌筹码中进行细粒度的市场细分是不值得的。）

(IDK the details. Maybe the Bronze/Silver chips are weaker, but their marketing department decided it wasn't worth doing finer-grained market segmentation within the Gold chips.)

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