QuartusII综合：枚举类型到状态信号（编码） [英] QuartusII Synthesis: Enumerated type to State signals (encoding)

问题描述

我正在设计SystemVerilog中的FSM，以便通过QuartusII（14.1）工具进行综合以安装在Altera FPGA上。我使用一个枚举声明使代码更合理：

  typedef枚举逻辑[7：0] {CMD_INIT，
 CMD_WAIT，
 CMD_DECODE，
 CMD_ILLEGAL，
 CMD_CMD0，
 ...} cmd_st； 
 ... 
 cmd_st cs，ncs; 
 ... 
  

每当Quartus合成此状态机时，它似乎都会创建一个尽管该类型的逻辑[7：0] 部分仍能进行热编码。像这样，当我将状态添加到SignalTap时，我将所有状态作为信号1位变量（ cs.CMD_INIT ， cs.CMD_WAIT 等）。尽管这通常非常有用，但由于我需要一次看到一堆这些状态和一些超值，所以我用完了所有这些状态的片上存储器（其中有8种以上；例如50种） +）。因此，将它们全部添加到SignalTap会占用大量内存。但是，如果我可以放下 cs 的8位值，我将有足够的空间来放置其他东西。

我无法弄清楚如何使Quartus不对FSM使用1-hot编码。我尝试将设置（设置->编译器设置->高级设置（合成...）->状态机处理）更改为最小位，用户编码和顺序以及一些状态的附加值：

  typedef枚举逻辑[7：0] {CMD_INIT = 8'd0，
 CMD_WAIT = 8'd1，
 CMD_DECODE = 8'd2，
 CMD_ILLEGAL = 8'd3，
 CMD_CMD0，
  

（请注意，并非所有人都可以，因为一堆我可能会在中间添加更多内容）

我不确定该怎么做，以便SignalTap只能看到状态的8位（这可能可以追溯到让Quartus将该FSM作为顺序而不是1hot编码进行合成）

解决方案

您可以使用综合编译指示来指导Quartus对状态变量使用特定的编码方案。此页面为您提供有关如何使用顺序编码对状态机进行编码的详细信息，从而避免使用默认的一键编码。

I am designing an FSM in SystemVerilog for synthesis through the QuartusII (14.1) tool to put on an Altera FPGA. I am using an enum declaration to make the code much more reasonable:

typedef enum logic [7:0] { CMD_INIT,
                           CMD_WAIT,
                           CMD_DECODE,
                           CMD_ILLEGAL,
                           CMD_CMD0,
                           ... } cmd_st;
...
cmd_st cs, ncs;
...

Whenever Quartus synthesized this state machine, it seems to create a one-hot encoding despite the logic [7:0] part of the type. As in, when I got to add the states to SignalTap, I get all of the states as a signal 1-bit variable (cs.CMD_INIT, cs.CMD_WAIT, etc). While this is usually pretty useful, as I need to see a bunch of these states and some over values at once, I am running out of on-chip memory to contain all of these states (there are well over 8 of them; like 50+). So adding all of them to SignalTap takes ALOT of this memory; but if I could just put down the 8-bit value for cs, I would have plenty of space for other things.

I cant figure out how to get Quartus to NOT use the 1-hot encoding for the FSM. I have tried changing the settings (Settings->Compiler Settings->Advance Settings (Synthesis...)->State Machine Processing) to Minial Bits, User Encoding and Sequential, as well as added values for a few of the states:

typedef enum logic [7:0] { CMD_INIT           = 8'd0,
                           CMD_WAIT           = 8'd1,
                           CMD_DECODE         = 8'd2,
                           CMD_ILLEGAL        = 8'd3,
                           CMD_CMD0,

(Note, not all of them as there are a bunch of I might add even more in the middle)

Im not sure what else to do so that SignalTap sees only 8-bits for the states (which probably goes back to getting Quartus to synthesize this FSM as sequential rather than 1hot encoding)

解决方案

You can use synthesis pragmas to guide Quartus to use a specific encoding scheme for the state variables. This page gives you details on how to encode state machines using "sequential" encoding thereby avoiding the default one-hot encoding.

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