如何生成异步重置Verilog总是会因凿而阻塞 [英] How to generate an asynchronous reset verilog always blocks with chisel

问题描述

在灵敏度列表中，凿子总是产生只有时钟的块:

Chisel generate always blocks with only clock in sensivity list :

always @posedge(clk) begin
  [...]
end

是否可以将Module配置为使用异步重置并生成像这样的always块?

Is it possible to configure Module to use an asynchronous reset and generate an always block like this ?

always @(posedge clk or posedge reset) begin
   [...]
end

推荐答案

自Chisel 3.2.0起，就支持同步，异步和抽象重置类型.根据显式指定或推断的重置类型，您将获得规范的同步或异步Verilog输出.

Since Chisel 3.2.0, there is support for synchronous, asynchronous, and abstract reset types. Based on the type of reset explicitly specified or inferred, you will get canonical synchronous or asynchronous Verilog output.

要尝试更全面地显示此内容，请考虑以下具有三个重置的MultiIOModule:

To try to show this more fully, consider the following MultiIOModule which has three resets:

• 具有抽象重置类型(这是抽象重置")的隐式reset输入
• 具有Bool类型(这是同步重置")的显式syncReset输入
• 具有AsyncReset类型的显式asyncReset输入(这是异步重置")

• The implicit reset input which has an abstract reset type (this is "abstract reset")
• The explicit syncReset input which has a Bool type (this is "synchronous reset")
• The explicit asyncReset input which has an AsyncReset type (this is "asynchronous reset")

使用withReset，然后可以将特定的复位连接用于设计中的不同寄存器:

Using withReset, specific reset connections can then be used for different registers in the design:

import chisel3._
import chisel3.stage.ChiselStage

class Foo extends MultiIOModule {
  val syncReset  = IO(Input(Bool()      ))
  val asyncReset = IO(Input(AsyncReset()))

  val in          = IO(Input( Bool()))
  val outAbstract = IO(Output(Bool()))
  val outSync     = IO(Output(Bool()))
  val outAsync    = IO(Output(Bool()))

  val regAbstract =                         RegNext(in, init=0.U)
  val regSync     = withReset(syncReset)  { RegNext(in, init=0.U) }
  val regAsync    = withReset(asyncReset) { RegNext(in, init=0.U) }

  outAbstract := regAbstract
  outSync     := regSync
  outAsync    := regAsync
}

然后使用以下命令编译时会生成以下Verilog:(new ChiselStage).emitVerilog(new Foo):

This then produces the following Verilog when compiled with: (new ChiselStage).emitVerilog(new Foo):

module Foo(
  input   clock,
  input   reset,
  input   syncReset,
  input   asyncReset,
  input   in,
  output  outAbstract,
  output  outSync,
  output  outAsync
);
  reg  regAbstract;
  reg  regSync;
  reg  regAsync;
  assign outAbstract = regAbstract;
  assign outSync = regSync;
  assign outAsync = regAsync;
  always @(posedge clock) begin
    if (reset) begin
      regAbstract <= 1'h0;
    end else begin
      regAbstract <= in;
    end
    if (syncReset) begin
      regSync <= 1'h0;
    end else begin
      regSync <= in;
    end
  end
  always @(posedge clock or posedge asyncReset) begin
    if (asyncReset) begin
      regAsync <= 1'h0;
    end else begin
      regAsync <= in;
    end
  end
endmodule

注意:在Chisel 3.2中，顶级抽象重置将始终设置为同步重置.在Chisel 3.3.0中，添加了两个特征:RequireSyncReset和RequireAsyncReset.这些可用于将连接到regAbstract的寄存器的复位类型从同步更改为异步.用(new ChiselStage).emitVerilog(new Foo with RequireAsyncReset)重新编译设计，将regAbstract逻辑更改为

Note: that in Chisel 3.2 the top-level abstract reset would always be set to synchronous reset. In Chisel 3.3.0, two traits were added: RequireSyncReset and RequireAsyncReset. These can be used to change the reset type of the register connected to regAbstract from synchronous to asynchronous. Recompiling the design with (new ChiselStage).emitVerilog(new Foo with RequireAsyncReset), changes the regAbstract logic to

always @(posedge clock or posedge reset) begin
  if (reset) begin
    regAbstract <= 1'h0;
  end else begin
    regAbstract <= in;
  end
end

有关更多信息， Chisel网站提供了有关重置的更多信息.

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