在Always块中使用For循环 [英] Use of For loop in always block

问题描述

我正在编写一个Verilog代码，用于计算十进制数中的位数.在下面的代码中，我将c的值初始化为等于a. 我能够正确获得仿真结果，但无法进行合成，并且错误是由于'c = a'引起的.如何摆脱错误?还有其他逻辑可以计算位数吗?

I am writing a Verilog code for calculating the number of digits in a decimal number. In the code below I have initialised the value of c to be equal to a. I was able to get the simulation results correctly but unable to syntesise and the error is due to 'c=a'. How can I get rid of the error ? Is there any other logic to calculate the number of digits ?

Error: [Synth 8-3380] loop condition does not converge after 2000 iterations 

代码:-

module numdigits(a,b);
parameter n=100;
input [0:n-1] a;
output reg [0:n-1]b;   //THIS MODULE COUNTS THE NUMBER OF DIGITS IN DECIMAL FORM
reg [0:n-1] d,c;
always @(*)
begin 
    d=0;
    for(c=a;c>0;c=c/10)
    begin
    d=d+1;
    end
    b=d;
end 
endmodule

推荐答案

为使for循环可合成，它必须为 static :即最大迭代次数循环必须是固定的.考虑到a具有固定的位数，您的循环似乎有最大的迭代次数，但请记住，合成器不会模拟您的代码，因此它不能告诉您.

In order for a for loop to be synthesisable, it must be static: that is, the maximum number of iterations round the loop must be fixed. It might seem that there is a maximum number of iterations of your loop, given that a has a fixed number of bits, but remember that your synthesiser doesn't simulate your code, so it cannot tell that.

您需要重构代码；您需要以某种方式编写它，以便最大数量的循环迭代是固定的.换句话说，循环的迭代次数必须是固定的，但是您可以根据需要提前跳出(使用disable语句).

You need to refactor your code; you need to write it in such a way so that the maximum number of loop iterations is fixed. In other words, the number of iterations of the loop must be fixed, but you can jump out early if you wish (using the disable statement).

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