如何使用Xilinx Division IP内核 [英] How to use the Xilinx Division IP Core

问题描述

我正在用VHDL编写代码，以将其合成到XilinX FPGA上.我通常使用GHDL模拟我的测试平台.我需要利用XilinX划分核心才能对变量进行划分，但是我不确定如何执行此操作，因为XilinX文档中似乎没有示例.我是否必须使用XilinX软件为分频器生成VHDL组件?还是XilinX暗中了解分频器意味着使用IP内核?如果我的第二条陈述是正确的，我将如何使用GHDL进行仿真，还是必须使用XilinX仿真工具?我真的可以举一个使用XilinX除法器内核来实现按变量除法的最小示例.像这样的东西:

I am writing code in VHDL to be synthesised onto a XilinX FPGA. I typically use GHDL to simulate my testbenches. I need to make use of the XilinX division core in order to divide by a variable however I am not sure how to do this as there appear to be no examples in the XilinX documentation. Do I have to use the XilinX software to generate the VHDL component for the divider? Or does XilinX implicitly understand that divider means using the IP core? If my 2nd statement is true how would I go about simulating this with GHDL or would I have to use a XilinX simulation tool? I could really do with a minimal example of using the XilinX divider core to implement division by a variable e.g. something like this:

library ieee;      
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;

entity DividingExample is
  port (
    clk : in std_logic;
    reset : in std_logic;
    InputSignal : in std_logic_vector(15 downto 0);
    OutputSignal : out std_logic_vector(15 downto 0)
    );
end DividingExample;

architecture behaviour of DividingExample is
-- declarations
  signal numerator : integer;
begin
-- behaviour
  process(clk)
  begin
    if(rising_edge(clk)) then
      if(reset = '1') then
        -- reset values
        numerator <= 1000;  
      else
        -- calculate value to be output
        OutputSignal <= numerator/to_integer(signed(InputSignal))
    end if;
  end if;
end process;
end behaviour;

该示例代码显然无法工作，因为未为整数数据类型定义除("/"运算符).我该怎么办?

This example code obviously doesn't work as division (the '/' operator) is not defined for the integer datatype. How might I go about this?

推荐答案

我最终编写了自己的部门代码，该部门代码比使用XilinX的IP Core显着更快，更容易实现.我在此处中使用了详细的二进制除法算法，并编写了以下VHDL代码对于有符号的32位除法:

I ended up writing my own division code, which was significantly quicker and easier to implement than using XilinX's IP Core. I used the binary division algorithm detailed here and wrote the following VHDL code for a signed 32 bit division:

  function Divide(N : signed(31 downto 0); D : signed(31 downto 0)) return signed is                                                                                                                    
    variable Q : signed(31 downto 0) := to_signed(0, 32);                                                      
    variable R : signed(31 downto 0) := to_signed(0, 32);                                                      
    variable l : line;                                                                                           
    constant N_Abs : signed(31 downto 0) := abs(N);                                                             
    constant D_Abs : signed(31 downto 0) := abs(D);                                                             
  begin                                                                                                          
    -- behaviour                                                                                                 
    for i in N_Abs'high downto 0 loop                                                                            
      R := shift_left(R, 1);                                                                                     
      R(0) := N_Abs(i);                                                                                          
      if R >= D_Abs then                                                                                         
        R := R - D;                                                                                              
        Q(i) := '1';                                                                                             
      end if;                                                                                                    
    end loop;                                                                                                    

    if ((N < 0 and D > 0) or (N > 0 and D < 0)) then                                                             
      return -Q;                                                                                                 
    else                                                                                                         
      return Q;                                                                                                  
    end if;                                                                                                      
  end function;

这篇关于如何使用Xilinx Division IP内核的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！