如何在Gnu Make文件中全局运行一些命令 [英] How to run some commands globally in a Gnu Make file

问题描述

我有一个gnu Makefile，它通过环境变量收集版本信息.现在，我想在使用gnumake语法构建任何目标之前全局执行操作".作为伪代码，这意味着:

I have a gnu Makefile that collects version information through environment variables. Now, I want to do "something" globally before any target is built using the gnumake syntax. As pseudo code, this means:

• 存在指定文件时，将其删除
• 遍历字符串数组并将其值放入指定的文件

我尝试过:

$(shell if exist $(subst /,\,$(products)filenames.h) del /F/Q $(subst /,\,$(products)filenames.h))
$(foreach Item, $(EnvFilenames), @echo $(Item) >> $(subst /,\,$(products)filenames.h))

这给了我一个错误:

C:\temp\Makefile.mak:72: *** missing separator.  Stop.

其中第72行是$(shell ...行.如果我将其放在define部分:

where Line 72 is the $(shell ... line. If I put this in a define section:

define foobar
$(shell if exist $(subst /,\,$(products)filenames.h) del /F/Q $(subst /,\,$(products)filenames.h))
$(foreach Item, $(EnvFilenames), @echo $(Item) >> $(subst /,\,$(products)filenames.h))
endef

并将其称为目标，它可以正常运行:

and call this for a target, it runs fine:

$(products)$test.o : test.c $(commons)
$(call foobar)
$(cc) $(cflags_m) test.c -o$@ 

并执行应有的操作...但是，只要我想从另一个define内部调用它，它就会再次失败，并缺少分隔符.

and does what it should... but as soon as I want to call it from inside of another define, it fails again with a missing seperator.

这是什么意思，我该如何解决?

What does it mean and how can I fix it?

编译是在Win32平台上进行的，不必是多平台的.

Compilation takes place on a Win32 platform and does not have to be multi-platform.

推荐答案

如果每个Make调用足够一次，则可以将其放入全局分配中.

If once per Make invocation is sufficient, you could put it in a global assignment.

# Ignore the value, calling for side effects
IGNORE := $(shell commands with side effects)

我会建议不要使用这种黑客，但我可以想象一下可能会派上用场的情况.

I would recommend against this hack, but I can imagine situations where it might come in handy.

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