超线程CPU是实现并行性还是仅并发性? [英] Does a hyperthreading CPU implement parallelism or just concurrency?
问题描述
超线程CPU是实现并行性还是仅实现并发性(上下文切换)?
我的猜测不是并行性，而是上下文切换带来的并发性.
具有超线程功能的单个物理CPU 内核在操作系统中显示为两个逻辑CPU .该CPU仍然是单个CPU，因此有点作弊" -操作系统在每个内核中看到两个CPU，而实际的CPU硬件仅具有一套执行资源.CPU假装它具有比其更多的内核，并且它使用自己的逻辑来加速程序执行.超线程允许两个逻辑CPU内核共享物理执行资源.这样可以加快速度-例如，如果一个虚拟CPU停滞并等待，另一虚拟CPU可以借用其执行资源.同样，可以将空闲资源用于同时执行其他任务.超线程可以帮助您加快系统速度，但远不及拥有更多内核.除非您考虑采用超标量架构，否则在单核处理器上真正意义上的并行性(如GPGPU架构或多个物理内核中的独立执行)不可能实现.
发件人::
超线程技术使单个物理处理器看起来像是多个逻辑处理器.每个逻辑处理器都有一个体系结构状态副本，并且这些处理器共享一组物理执行资源.从软件或体系结构的角度来看，这意味着操作系统和用户程序可以调度进程或就像在多处理器系统中的常规物理处理器上一样，将逻辑线程连接到逻辑处理器.从微体系结构的角度来看，这意味着逻辑处理器中的指令将持久存在并在共享执行资源上同时执行.Netburst微体系结构上的超线程技术实现在每个物理处理器上都有两个逻辑处理器.图1显示了具有超线程技术功能的处理器的概念图.每个逻辑处理器维护完整的体系结构状态集.体系结构状态由寄存器(包括通用寄存器)，用于控制的寄存器，高级可编程中断控制器(APIC)以及用于机器状态的寄存器组成.从软件角度看，架构状态的重复使每个物理处理器看起来像是两个处理器.每个逻辑处理器都有自己的中断控制器或APIC，该API只能处理发送到其特定逻辑处理器的中断
注意:对于使用超标量内核(即一个内核每个周期可以执行多个操作)的同时多线程，执行过程有很大不同.
Does a hyperthreading CPU implement parallelism or just concurrency (context switching)?
My guess is no parallelism, only concurrency by context switching.
A single physical CPU core with hyperthreading appears as two logical CPUs to an operating system. The CPU is still a single CPU, so it’s "cheating" a bit — while the operating system sees two CPUs for each core, the actual CPU hardware only has a single set of execution resources for each core. The CPU pretends it has more cores than it does, and it uses its own logic to speed up program execution. Hyper-threading allows the two logical CPU cores to share physical execution resources. This can speed things up somewhat — for example, if one virtual CPU is stalled and waiting, the other virtual CPU can borrow its execution resources. Also, free resources can be utilized for simultaneous execution of other tasks. Hyper-threading can help speed your system up, but it’s nowhere near as good as having additional cores. Parallelism in its real sense (independent execution as in GPGPU architecture or multiple physical cores), is not attainable on a single-core processor unless you are considering a superscalar architecture.
From: https://en.wikipedia.org/wiki/Superscalar_processor
Superscalar processors differ from multi-core processors in that the several execution units are not entire processors. A single processor is composed of finer-grained execution units such as the ALU, integer multiplier, integer shifter, FPU, etc. There may be multiple versions of each execution unit to enable execution of many instructions in parallel. This differs from a multi-core processor that concurrently processes instructions from multiple threads, one thread per processing unit (called "core"). It also differs from a pipelined processor, where the multiple instructions can concurrently be in various stages of execution, assembly-line fashion.
Hyper Threading technology makes a single physical processor appear to be multiple logical processors. There is one copy of the architectural state for each logical processor, and these processors share a single set of physical execution resources. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on conventional physical processors in a multiprocessor system. From a microarchitecture perspective, it means that instructions from logical processors will persist and execute simultaneously on shared execution resources. This can greatly improve processor resource utilization. The hyper threading technology implementation on the Netburst microarchitecture has two logical processors on each physical processor. Figure 1 shows a conceptual view of processors with hyperthreading technology capability. Each logical processor maintains a complete set of the architectural state. The architectural state consists of registers, including general-purpose registers, and those for control, the advanced programmable interrupt controller (APIC), and some for machine state. From a software perspective, duplication of the architectural state makes each physical processor appear to be two processors. Each logical processor has its own interrupt controller, or APIC, which handles just the interrupts sent to its specific logical processor.
Note: For simultaneous multithreading using a superscalar core (i.e., one that can issue more than one operation per cycle), the execution process is significantly different.
这篇关于超线程CPU是实现并行性还是仅并发性?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
