带RGB开关滤镜的HDMI直通 [英] HDMI Pass Through with RGB Switch Filter
问题描述
我对VHDL和FPGA还是很陌生，并且遇到了麻烦.我目前正在使用zybo z7-10上的视频过滤器，并开始使用此指南在板上创建HDMI直通: https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.34188391.796043983.1579510279-2100398226.1578999679
I'm very new to VHDL and FPGAs, and have hit a rock. Im currently working on video filters on the zybo z7-10, and started off using this guide to create a HDMI passthrough on the board: https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.34188391.796043983.1579510279-2100398226.1578999679
因此，在完成所有工作后，我想要做的就是能够实现视频输出.为此，我尝试将最后8位的rgb 24位向量设置为0，从输出中删除所有蓝色.如果我尝试以下代码(带有或不带有过程块)，则在"if"语句行上会收到语法错误
So after getting that working all i want to do is be able to effect the video output. To do this, I tried to set the rgb 24 bit vectors last 8 bits to 0, removing all blue from the output. If i try the following code (with or without the process block) i get a syntax error on the "if" statement line
process is
begin
if sw ='0' then
vid_pData(7 downto 0) <= sw
end if;
end process;
问题是我似乎无法将其放在代码中的任何位置而不会导致错误.有人可以解释这里发生了什么吗?
The issue is I don't seem to be able to put this anywhere in the code without causing an error. Can someone explain what's happening here?
下面的完整代码:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity hdmi_pass_top is
Port (
sysclk_i : in std_logic; -- 125MH System Clock Input
async_reset_i : in std_logic; -- Reset switch on board
-- HDMI In/Rx
tmds_rx_clk_p_i : in std_logic;
tmds_rx_clk_n_i : in std_logic;
tmds_rx_data_p_i : in std_logic_vector(2 downto 0);
tmds_rx_data_n_i : in std_logic_vector(2 downto 0);
hdmi_rx_hpd_o : out std_logic := '1'; -- HPD must be driven
-- I2C
sda_io : inout std_logic;
scl_io : inout std_logic;
-- HDMI Out/Tx
tmds_tx_clk_p_o : out std_logic;
tmds_tx_clk_n_o : out std_logic;
tmds_tx_data_p_o : out std_logic_vector(2 downto 0);
tmds_tx_data_n_o : out std_logic_vector(2 downto 0);
sw : in std_logic
);
end hdmi_pass_top;
architecture hdmi_pass_top_arc of hdmi_pass_top is
component dvi2rgb_0
port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
RefClk : in std_logic;
aRst : in std_logic;
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic;
aPixelClkLckd : out std_logic;
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_T : out std_logic;
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_T : out std_logic;
pRst : in std_logic
);
end component;
component rgb2dvi_0
PORT (
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
aRst : in std_logic;
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic
);
end component;
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic;
clk_in1 : in std_logic
);
end component;
signal vid_pData : std_logic_vector(23 downto 0);
signal vid_pVDE : std_logic;
signal vid_pHSync : std_logic;
signal vid_pVSync : std_logic;
signal pixelclk : std_logic;
signal locked : std_logic;
signal clk_200M : std_logic;
signal pixel_clk_sync_rst : std_logic;
signal sda_i : std_logic;
signal sda_o : std_logic;
signal sda_t : std_logic;
signal scl_i : std_logic;
signal scl_o : std_logic;
signal scl_t : std_logic;
begin
clkwiz_inst : clk_wiz_0
port map (
-- Clock out ports
clk_out1 => clk_200M,
-- Status and control signals
reset => async_reset_i,
locked => locked,
-- Clock in ports
clk_in1 => sysclk_i
);
dvi2rgb_inst : dvi2rgb_0
port map (
TMDS_Clk_p => tmds_rx_clk_p_i,
TMDS_Clk_n => tmds_rx_clk_n_i,
TMDS_Data_p => tmds_rx_data_p_i,
TMDS_Data_n => tmds_rx_data_n_i,
RefClk => clk_200M,
aRst => async_reset_i, --Active high asynchronous RefClk reset
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk,
aPixelClkLckd => open, --
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
pRst => '0' -- Active high PixelClk synchronous reset
);
SDA_IOBUF_inst: IOBUF
generic map(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map(
O => sda_i, -- Buffer output
IO => sda_io, -- Buffer inout port(connect directly to top-level port)
I => sda_o, -- Bufferinput
T => sda_t -- 3-state enable input,high=input,low=output
);
SCL_IOBUF_inst: IOBUF
generic map(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map(
O => scl_i, -- Buffer output
IO => scl_io, -- Buffer inout port(connect directly to top-level port)
I => scl_o, -- Buffer input
T => scl_t -- 3-state enable input,high=input,low=output
);
rgb2dvi_inst : rgb2dvi_0
port map (
TMDS_Clk_p => tmds_tx_clk_p_o,
TMDS_Clk_n => tmds_tx_clk_n_o,
TMDS_Data_p => tmds_tx_data_p_o,
TMDS_Data_n => tmds_tx_data_n_o,
aRst => async_reset_i,
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk
);
end hdmi_pass_top_arc;
将我的if语句更改为
changed my if statement to
vid_pData(7 downto 0) <= "00000000" when sw = '0';
，它消除了错误，但实现失败.失败是:
and it got rid of the error but the implementation failed. The failure is:
[DRC MDRV-1]多个驱动程序网络:网络dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/vid_pData [0]有多个驱动程序:vid_pData_reg [0]/Q，和dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/poData_reg [0]/Q.
[DRC MDRV-1] Multiple Driver Nets: Net dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/vid_pData[0] has multiple drivers: vid_pData_reg[0]/Q, and dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/poData_reg[0]/Q.
推荐答案
您不是在编写软件，而是在设计硬件.您的额外代码驱动信号 vid_pData .因此，组件 dvi2rgb_0 也是如此.因此，您在该信号上有两个驱动程序.换句话说，就是短路.
You're not writing software, you're designing hardware. Your extra code drives signal vid_pData. So, does component dvi2rgb_0. So you have two drivers on that signal. A short circuit in other words.
此外，如果 sw 不等于'0'，您也不会说 vid_pData 应该采用什么值.因此，您将在硬件中遇到闩锁.(Google推断出闩锁".)
Also, you do not say what value vid_pData should take if sw is not equal to '0'. Therefore, you will get latches in your hardware. (Google "inferring a latch".)
您需要一个新信号，例如:
You need a new signal, eg:
signal vid_pData_new : std_logic_vector(23 downto 0);
然后您需要为 sw 都分配一个等于'0'和'1'的值，否则您将得到一个锁存器:
then you need to assign a value for both sw equals '0' and '1', otherwise you will get a latch:
vid_pData_new(7 downto 0) <= vid_pData(23 downto 8) & "00000000" when sw = '0' else vid_pData;
& 运算符是 concatenation 运算符.最后，您需要使用新信号来驱动 rgb2dvi_0 组件:
The & operator is the concatenation operator. Finally, you need to drive component rgb2dvi_0 with your new signal:
rgb2dvi_inst : rgb2dvi_0
port map (
TMDS_Clk_p => tmds_tx_clk_p_o,
TMDS_Clk_n => tmds_tx_clk_n_o,
TMDS_Data_p => tmds_tx_data_p_o,
TMDS_Data_n => tmds_tx_data_n_o,
aRst => async_reset_i,
vid_pData => vid_pData_new, -- <-----------------
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk
);
您能看到这里做了什么吗?我们已经插入了一个新的硬件来驱动新信号 vid_pData_new ，并为 sw 的两个可能值指定了其值.我们必须执行此操作，否则我们将获得闩锁.我们正在设计硬件，不是编写软件.
Can you see what has been done here? We have inserted a new piece of hardware that drives the new signal vid_pData_new and have specified its value for both possible values of sw. We must do this, otherwise we will get latches. We are designing hardware, not writing software.
这篇关于带RGB开关滤镜的HDMI直通的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
