有关x86 LAPIC系统上的消息信号中断(MSI)的问题 [英] Question about Message Signaled Interrupts (MSI) on x86 LAPIC system
问题描述
我正在编写一个内核，并计划对PCI设备使用MSI中断.
Hi I'm writing a kernel and plan to use MSI interrupt for PCI devices.
但是，我对文档也很困惑.
However, I'm also quite confused by the documentations.
我对MSI的理解如下:
My understanding about MSI are as follow:
从PCI设备的角度来看:
From PCI device point of view:
- 文档表明我需要找到Capabillty ID = 0x05来定位3个寄存器:消息控制(MCR)，消息地址(MAR)和消息数据(MDR)寄存器
- MCR为MSI中断提供控制功能，
- MAR提供PCI设备的物理地址一旦中断发生就会写
- MDR形成它将写入物理地址的实际数据
从CPU角度来看:
-
文档显示消息地址寄存器的顶部固定为0xFEE，后跟目标ID(LAPIC ID)和其他控制位，如下所示:
Documentation shows that Message Address register contains fixed top of 0xFEE, and following by destination ID (LAPIC ID) and other controlling bits as follow:
消息数据寄存器将包含以下信息，包括中断向量:
The Message Data register will contain the following information, including the interrupt vector:
阅读所有这些内容之后，我在考虑如果APIC_ID为0x0h，那么消息地址是否会与本地APIC内存映射冲突?尽管保留了FEE00000〜FEE00010的地址.
After reading all of these, I am thinking if the APIC_ID is 0x0h would the Message Address conflict with the Local APIC memory mapping? Although the address of FEE00000~FEE00010 are reserved.
此外，MDR中的向量号是否确实与IDT向量号相对应.换句话说，如果我将MAR = 0xFEE0000C(目标ID = 0，使用逻辑APIC ID)和MDR = 0x0032(边沿触发，Vector = 50)并启用MSI中断，则一旦设备发出中断，CPU就会相应运行IDT [50]指向的功能?之后，我将0h写入EOI寄存器以结束它?
In addition, is it true that the vector number in MDR is corresponding to the IDT vector number. In other words, if I put MAR = 0xFEE0000C (Destination ID = 0, Using logical APIC ID) and MDR = 0x0032 (edge trigger, Vector = 50) and enable the MSI interrupt, then once the device issues an interrupt CPU would correspondingly run the function pointed by IDT[50]? After that I write 0h to EOI register to end it?
最后，根据文档，不使用MAR的高32位吗?有人可以帮忙吗?
Finally, according to the documentation, the upper 32 bit of MAR is not used? Can anyone help on this?
非常感谢！
推荐答案
您对如何在PCI(或PCIe)设备中检测和编程MSI的理解是正确的.*消息地址控制目标地址(中断发送到哪个CPU)，而消息数据包含向量号.对于正常中断，消息数据的所有位都应为0，但低8位除外，该低8位包含向量.该向量是IDT的索引，因此，如果消息数据为0x0032，则通过IDT的条目50传递中断.**
Your understanding of how to detect and program MSI in a PCI (or PCIe) device is correct.* The message address controls the destination (which CPU the interrupt is sent to), while the message data contains the vector number. For normal interrupts, all bits of the message data should be 0 except for the low 8 bits, which contain the vector. The vector is an index into the IDT, so if the message data is 0x0032, the interrupt is delivered through entry 50 of the IDT.**
如果中断消息中的目标ID为0，则MSI的消息地址确实与本地APIC的默认地址匹配，但不会冲突，因为APIC只能由CPU写入，而MSI只能由设备编写.
If the Destination ID in an interrupt message is 0, the Message Address of the MSI does match the default address of the local APIC, but they do not conflict, because the APIC can only be written by the CPU and MSIs can only be written by devices.
在x86平台上，消息地址的高32位必须为0.这可以通过将消息地址的高位设置为0或通过将设备编程为使用32位消息地址来完成(其中如果不使用高位消息地址寄存器).PCI规范旨在与使用64位MSI地址的系统一起使用，但是x86系统从不使用消息地址的高32位.
On x86 platforms, the upper 32 bits of the message address must be 0. This can be done by setting the upper part of the message address to 0 or by programming the device to use a 32-bit message address (in which case the upper message address register is not used). The PCI spec was designed to work with systems where 64-bit MSI addresses are used, but x86 systems never use the upper 32 bits of the message address.
通过写入APIC_BASE MSR重新编程APIC基址不会影响MSI所用的地址范围；始终为0xFEExxxxx.
Reprogramming the APIC base address by writing to the APIC_BASE MSR does not affect the address range used for MSI; it is always 0xFEExxxxx.
*您还应该查看MSI-X功能，因为某些设备支持MSI-X，但不支持MSI.MSI-X更加灵活，这不可避免地使其更加复杂.
* You should also look at the MSI-X capability, because some devices support MSI-X but not MSI. MSI-X is a bit more flexible, which inevitably makes it a bit more complicated.
**使用MSI功能时，消息数据与消息数据寄存器(MDR)中的值不完全相同.MSI功能允许设备使用多个连续向量.当设备发送中断消息时，它会根据设备内部的中断原因用不同的值替换MDR的低位.
** When using the MSI capability, the message data isn't exactly the value in the Message Data Register (MDR). The MSI capability allows the device to use several contiguous vectors. When the device sends an interrupt message, it replaces the low bits of the MDR with a different value depending on the interrupt cause within the device.
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