是ARM的Cortex-A8管线13级或14级？ [英] Is ARM Cortex-A8 pipeline 13 stage or 14 stage?

问题描述

如果你看到ARM的一个<给出的ARM Cortex-A8的这种流行的管线图一href=\"http://esd.et.ntust.edu.tw/downloads/2012_embeddedApplication/ARM%20Archi%20RichardGrisenthwaite.pdf\"相对=nofollow> presentations 。很显然，在取指令阶段需要3个周期，但在第一周期的排序的打折的。但为什么？有什么想法？

感谢您......

解决方案

从某种程度上隐藏的文件上的 Cortex A8的：

  

    

的提取管线开始其中产生一个新的虚拟地址F0阶段。这个
    地址可以是由一个分支prediction为一个previous提供一个分支目标地址
    指令，或者如果有使这个周期没有prediction，下一地址将被计算
    顺序地从在previous循环使用的提取地址。需要注意的是基频读取级不算作在13级主整数流水线的正式阶段。 这是因为ARM处理器的管道一直计算与指令高速缓存访​​问的第一阶段开始阶段。

  

If you see this popular pipeline diagram of ARM Cortex-A8 given in one of ARM presentations. It is clear that the instruction fetch stage takes 3 cycles, yet the first cycle is sort of discounted. But, why? Any thoughts?

Thank you...

解决方案

From somewhat hidden paper on Cortex A8:

The fetch pipeline begins with the F0 stage where a new virtual address is generated. This address can either be a branch target address provided by a branch prediction for a previous instruction, or if there is no prediction made this cycle, the next address will be calculated sequentially from the fetch address used in the previous cycle. Note that the F0 Fetch stage is not counted as an official stage in the 13 stage main integer pipeline. This is because ARM processor pipelines have always counted stages beginning with the Instruction Cache access as the first stage.

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