是什么在臂组件对应的preFIX的＆QUOT;锁定＆QUOT;在86？ [英] What's the corresponding prefix in arm assembly for "lock" in x86?

问题描述

我有一个x86汇编code：

I have a x86 assembly code:

unsigned int oldval;

__asm__ __volatile__ (
"movl   $1, %0  \n"
"lock xaddl %0, (%1)    \n"
: "=a" (oldval) :  "b" (n))l;

return oldval;

和我想它翻译成臂总成。是否有臂总成任何preFIX，做同样的事情锁在这里？

and I want to translate it into arm assembly. Is there any prefix in arm assembly that does the same thing as "lock" here?

推荐答案

我不知道ARM，但粉饰说明书中，下列应接近你的原子交换和相加：

I don't know ARM, but from glossing over the manual, the following should approximate your atomic exchange-and-add:

foo:
    LDREX R1, [R0]         ;  R0 is "n", load linked
    ADD   R2, R1, 1        ;  R2 = R1 + 1
    STREX R3, R2, [R0]     ;  store conditionally, R3 = 0 if and only if success
    CBNZ  R3, foo          ;  on failure, try again

    ;; now return R1 to "oldval"

不同于x86，它会出现这种code可能需要任意长的成功，但我不知道是否有任何保证，这将最终取得成功。

Unlike on x86, it would appear that this code could take arbitrarily long to succeed, but I'm not sure whether there are any guarantees that this will eventually succeed.

不过，请注意，ARM的方法是比较安全的，因为有条件的商店将成功precisely时，它应该。相比之下，您的x86 code（看起来像一个内核的自旋锁拍摄？）只是增加了一个 * N 和试验是否达到原 * N 为零。如果有足够的线程试图同时此，那么 * N 可以溢出和为零，即使你没有获准参加锁。

However, note that the ARM approach is safer, since the conditional store will success precisely when it should. By contrast, your x86 code (which looks like taken from a kernel spin lock?) just adds one to *n and tests whether the original *n was zero. If enough threads attempt this concurrently, then *n can overflow and be zero even though you weren't allowed to take the lock.

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