对于ARM，为什么一个STM指令通常比多个STR指令更快？ [英] For ARM, why a single STM instruction is generally faster than multiple STR instructions?

问题描述

这是否与一些prefetch技术？
或DDR访问时序特性？

Is it related to some prefetch technology? Or with DDR access timing characteristics?

推荐答案

这个都用的ARMv5TE开始的路径写入缓冲器和L1高速缓存为64bit宽以容纳LDRD / STRD指令。这使得STM写出每个周期两个寄存器。

IIRC starting with ARMv5TE the path to the write buffer and the L1 caches is 64bit wide to accomodate the LDRD/STRD instructions. This allows STM to write two registers per cycle.

您还可以节省一点L1指令缓存，并且只使用一个在双核问题的管道，这也是一个额外的收益。

You'll also save a bit of L1 instruction-cache and use only one pipeline on dual-issue cores, which is also an additional gain.

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