UVM:驱动程序和程序分配的非法组合警告 [英] UVM: illegal combination of driver and procedural assignment warning

问题描述

我的芯片中有一个小块的 UVM 测试台.其中有一个带有驱动程序的代理，可以在虚拟接口上驱动数据，如下所示:

I have a UVM testbench for a small block in my chip. In this there is an agent with a driver that drives data on a virtual interface which looks something like this:

interface my_if (input bit clk);

  logic [3:0] opcode;

  // Clocking block for the driver
  clocking drvClk @(posedge clk);
    output opcode;
  endclocking

  // Clocking block for the monitor      
  clocking monClk @(posedge clk);
    input opcode;
  endclocking

endinterface

我在我的驱动程序中使用这个接口是这样的:

I use this interface in my driver like this:

class my_driver extends uvm_driver #(my_tr);
  my_if vif;
  ...
  virtual task run_phase(uvm_phase phase);
    super.run_phase(phase);

    forever begin
      seq_item_port.get_next_item(req);

      // Drive the transaction onto the interface
      // and wait for next clock
      vif.opcode <= req.opcode;
      @(vif.drvClk);

      seq_item_port.item_done();
    end
  endtask
endclass

据我所知，这是推荐的做事方式，而且效果很好.当我将此代理集成到更高级别的测试平台时，问题就出现了.在这种情况下，代理现在是被动的，并且驱动程序没有构建.我将操作码值分配给接口，以便监视器可以观察它.这是我的顶级线束的片段:

As far as i can tell, this is the recommended way of doing things, and it works well. The problem arises when I integrate this agent into a higher level testbench. In that case the agent is now passive and the driver is not built. I am assigning the opcode value to the interface so the monitor can observe it. Here is a snippet of my top level wire harness:

module my_top();
  bit clk = 0;

  always #5 clk = !clk;

  // instantiate the interface
  my_if my_if_inst(.clk(clk));

  // instantiate my dut
  my_dut dut(...);

  // pull out the internal opcode signal and assign it
  // to the interface
  assign my_if_inst.opcode = dut.submodule.opcode;

  // Set the virtual interface inside the agent
  initial begin
    uvm_config_db#(virtual my_if)::set(uvm_root::get(),"uvm_test_top.tb.env.my_agent", "vif", my_if_inst);
  end 
endmodule

当我在 NC 中运行它时，我收到一个警告:

When I run this in NC I get a warning:

ncelab: *W,ICPAVW: Illegal combination of driver and procedural assignment to variable opcode detected (output clockvar found in clocking block)

这是有道理的，因为接口将此信号定义为 drvClk 块的输出，而我正在顶层进行分配.我可以忽略这个警告(代码工作得很好)，但我宁愿以一种运行干净的方式对其进行编码.推荐的方法是什么?我摆脱了驱动程序的计时块，这有效，但我认为如果我这样做，我就为比赛条件做好了准备.

This makes sense since the interface defines this signal as an output for the drvClk block and I am doing an assignment at the top level. I can just ignore this warning (the code works just fine) but I would rather code it in a way that it runs cleanly. What is the recommended way to do this? I got rid of the clocking block for the driver and that works, but I think I am setting myself up for race conditions if I do that.

推荐答案

Easy;使操作码成为界面中的 wire.

Easy; make opcode a wire in your interface.

像对待双向信号一样对待操作码.请参阅我关于此主题的 DVCon 论文.

Treat opcode the same as you would a bidirectional signal. See my DVCon paper on this subject.

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