SystemVerilog 动态访问子阵列 [英] SystemVerilog dynamically accessing subarray

问题描述

我在编译代码第 9 行时遇到错误，所以我不确定如何动态访问数组.我必须从接收到的 bytes 构建 logic [255:0].(看起来我必须查看 SystemVerilog 的数据类型 :().提前致谢.

I am getting an error to compile code line 9, so I am not sure how to dynamically access arrays. I have to build logic [255:0] from the received bytes. (Looks like I have to review data types of SystemVerilog :( ). Thanks in advance.

module test;

    task test_array (logic [7:0] B);
      static logic [255:0] l_ar_B;

      l_ar_B[7:0] = B;

      for(int i=0; i<32; i++)
        l_ar_B[(i*8+7) : (i*8)] = B; // Error-[IRIPS] Illegal range in part select
      $stop();

    endtask

    initial begin
      $display("Start");
      test_array(8'h11);
    end

endmodule

推荐答案

当使用带有 [M : N] 语法的范围选择时，M 和 N 必须是常量.您应该使用语法 [s +: W] 的部分选择寻址，其中 W 是宽度的常量，s 可以是指示起始位位置的变量.+: 自 IEEE Std 1364-2001 (Verilog 2001) 以来就存在.看使用 + 索引向量和数组:

When using the range selection with [M : N] syntax, M and N must be be constants. You should use part-select addressing with the syntax [s +: W], where W is a constant for the width and s can be a variable indicating the starting bit position. The +: been around since IEEE Std 1364-2001 (Verilog 2001). See Indexing vectors and arrays with +:

for(int i=0; i<32; i++)
  l_ar_B[(i*8) +: 8] = B;

既然你在做复制，你可以使用 l_ar_B = {32{B}}; 在一个步骤中得到相同的结果.

Since you are doing replication, you can use l_ar_B = {32{B}}; to get the same result in a singe step.

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