错误“不允许对非寄存器结果进行程序分配" [英] Error "procedural assignment to a non-register result is not permitted"

问题描述

我收到错误

<块引用>

[Synth 8-2576] 对非寄存器结果的程序赋值不是允许 ["lpm_mult.v":29]

我做错了什么?

模块 lpm_mult (dataa, datab,//被乘数，乘数sum,//部分和时钟，//流水线时钟clken,//时钟使能aclr,//异步清除结果//产品);输入时钟；输入时钟；输入 aclr;输入 [31:0] 数据a；输入 [31:0] 数据 b；输入 [63:0] 总和；输出 [63:0] 结果；总是@(clken 或posedge 时钟)开始如果 (1==clken) 开始分配结果 = dataa * datab;结尾结尾结束模块

解决方案

有更多问题然后给出错误消息.正如其他人已经指出的那样 result 应该被定义为 output reg [63:0] result;

其他问题不会产生编译错误；它们会产生不正确的行为并且无法合成.用代码:

<块引用>

总是@(clken 或posedge 时钟)开始如果 (1==clken) 开始分配结果 = dataa * datab;结尾结尾

• clken 是异步触发器；它不应该在敏感列表中.

• always 块内的assign 语句称为过程连续赋值.一旦分配被触发，它会在 dataa 或 datab 的任何变化(忽略 clken 和 >时钟).

  • 注意:IEEE 正在考虑贬低过程连续赋值，因此将来它可能会成为非法语法.IEEE Std 1800-2012 C.4.2 程序分配和取消赋值语句:

    <块引用>

    过程assign 和deassign 语句可能是设计错误的来源，也可能是工具实施的障碍.过程assign 和deassign 语句不提供其他方法无法完成的功能，以避免这些问题.因此，过程 assign 和 deassign 语句在弃用列表中.换句话说，IEEE Std 1800 的未来修订版可能不需要支持这些声明.当前的标准仍然需要工具来支持过程assign 和deassign 语句.但是，强烈建议用户迁移他们的代码以使用过程或连续分配的替代方法之一.

    常规的连续赋值(assign 在程序块之外)将保持合法的语法.
    Verilog 和 SystemVerilog 被 IEEE 正式与 IEEE Std 1800-2009 合并.

• 同步逻辑应该使用非阻塞(<=)分配.这是在同步逻辑块中阻塞 (=) 赋值的合法语法，但不是重新开始.在同步逻辑块中使用阻塞分配可能会导致模拟器中的竞争条件，从而导致 RTL 和合成电路之间的行为不匹配.

  • 注意:assign 语句必须使用阻塞赋值(非阻塞是非法语法).

您的代码应该类似于以下内容，以便在模拟中正确编译和运行:

<代码>...输出 reg [63:0] 结果；总是@(posedge 时钟)开始如果 (clken==1) 开始结果 <= 数据 a * 数据 b;结尾结尾

I'm getting the error

[Synth 8-2576] procedural assignment to a non-register result is not permitted ["lpm_mult.v":29]

What am i doing wrong?

module lpm_mult (
    dataa, datab,     // multiplicand,multiplier
    sum,              // partial sum 
    clock,            // pipeline clock
    clken,            // clock enable
    aclr,             // asynch clear
    result            // product
);

input  clock;
input  clken;
input  aclr;
input  [31:0] dataa;
input  [31:0] datab;
input  [63:0] sum;
output [63:0] result;

always @ (clken or posedge clock) begin
    if (1==clken) begin
        assign result = dataa * datab;
    end
end

endmodule

解决方案

There are more issues then then giving error message. As others have already pointed out result should be defined as output reg [63:0] result;

The other issues will not generate a compiling error; they are generating incorrect behavior and are unsynthesizable. With the code:

always @ (clken or posedge clock) begin
    if (1==clken) begin
        assign result = dataa * datab;
    end
end

• clken is asynchronous trigger; it should not be in the sensitivity list.

• An assign statement inside the always block is call a procedural continuous assignment. Once the assignment is triggered, it will be continuously and immediately updated on any change to dataa or datab (ignoring the conditions of clken and clock).

  • Note: IEEE is considering depreciating procedural continuous assignment, so in the future it will likely become illegal syntax. IEEE Std 1800-2012 C.4.2 Procedural assign and deassign statements:

    The procedural assign and deassign statements can be a source of design errors and can be an impediment to tool implementation. The procedural assign and deassign statements do not provide a capability that cannot be done by another method that avoids these problems. Therefore, the procedural assign and deassign statements are on a deprecation list. In other words, a future revision of IEEE Std 1800 might not require support for these statements. This current standard still requires tools to support the procedural assign and deassign statements. However, users are strongly encouraged to migrate their code to use one of the alternate methods of procedural or continuous assignments.

    Regular continuous assignments (assign outside of procedural block) will remain as legal legal syntax.
    Verilog and SystemVerilog were officially merged by IEEE with IEEE Std 1800-2009.

• Synchronous logic should use non-blocking (<=) assignments. It is legal syntax to blocking (=) assignments in synchronous logic blocks, but is it not recommenced. Using blocking assignments in synchronous logic blocks may cause race conditions in the simulator resulting in behavioral mismatch between RTL and synthesized circuit.

  • Note: assign statements must use blocking assignments (non-blocking is illegal syntax).

Your code should look something line the following to compile and behave correctly in simulation:

...
output reg [63:0] result;

always @ (posedge clock) begin
    if (clken==1) begin
        result <= dataa * datab;
    end
end

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