Verilog:公共总线实现问题 [英] Verilog: Common bus implementation issue

问题描述

我一直在用 Verilog 编写 16 位 RISC 微处理器，但我又遇到了另一个障碍.代码编写任务结束后，我尝试合成它.发现了几个偶然的错误，我修复了它们.然后繁荣，巨大的错误.

I've been coding a 16-bit RISC microprocessor in Verilog, and I've hit yet another hurdle. After the code writing task was over, I tried to synthesize it. Found a couple of accidental mistakes and I fixed them. Then boom, massive error.

该设计包含四个 16 位公共总线.出于某种原因，我从综合工具中收到这些总线的多个驱动程序错误.

The design comprises of four 16-bit common buses. For some reason, I'm getting a multiple driver error for these buses from the synthesis tool.

计算机的架构受到 Bill Buzzbee 的 Magic-1 的启发并且几乎完全相同，但不包括页表机制.这是 Bill 的原理图 PDF:点击此处.向下滚动到第 7 页的架构.

The architecture of the computer is inspired by and is almost exactly the same as the Magic-1 by Bill Buzzbee, excluding the Page Table mechanism. Here's Bill's schematics PDF: Click Here. Scroll down to page 7 for the architecture.

控制矩阵负责处理总线和驱动器，我绝对确定在任何给定实例中每条总线只有一个驱动器.我想知道这是否可能是问题所在，因为综合工具可能不知道这一点.

The control matrix is responsible for handling when the buses and driven, and I am absolutely sure that there is only one driver for each bus at any given instance. I was wondering whether this could be the problem, since the synthesis tool probably doesn't know this.

三态语句允许写入总线，例如:

Tri-state statements enable writing to a bus, for example:

assign io [width-1:0] = (re)?rd_out [width-1:0]:0; // Assign IO Port the value of memory at address add if re is true.

我忘了提，io 端口是双向的(inout)并且只是连接到总线.这段代码来自RAM，单端口.除了 RAM 之外的所有其他寄存器都有单独的输入和输出端口.

I forgot to mention, the io port is bidirectional (inout) and is simply connected to the bus. This piece of code is from the RAM, single port. All other registers other than the RAM have separate input and output ports.

控制矩阵在每个负沿更新一个 30 位状态，例如:

The control matrix updates a 30-bit state every negative edge, for example:

state [29:0] <= 30'b100000000010000000000000100000; // Initiate RAM Read, Read ALU, Write PC, Update Instruction Register (ins_reg).

控制矩阵相当小，因为在我花时间编写其余指令之前，我只编写了一条指令来测试设计.

The control matrix is rather small, since I only coded one instruction to test out the design before I spent time on coding the rest.

不幸的是，将整个代码复制粘贴到这里是不合逻辑的.

Unfortunately, it's illogical to copy-paste the entire code over here.

我已经考虑了好几天了，如果能指出正确的方向，我将不胜感激.

I've been pondering over this for quite a few days now, and pointing me over to the right direction would be much appreciated.

推荐答案

当re为低电平时，assign语句应该是浮动的(驱动Zs).

When re is low, the assign statement should be floating (driving Zs).

//                    enable ?   driving          :  floating
assign io [width-1:0] = (re) ? rd_out [width-1:0] : {width{1'bz}};

如果它正在驱动任何其他值，那么合成器会将其视为多路复用器而不是三态.这就是冲突驱动程序消息的来源.

If it is driving any other value then the synthesizer will treat is as a mux and not a tri-state. This is where the conflicting driver message come from.

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