系统Verilog-randomize()的实现 [英] system verilog - implementation of randomize()

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本文介绍了系统Verilog-randomize()的实现的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我必须在systemVerilog中实现randomize()函数,因为我使用的工具(模型sim)不支持此功能。

I have to implement randomize() function in systemVerilog because the tool I use (model sim) doesn't support this function.

我在具有以下成员的类:

I implemented a basic function in a class with the following member:

   bit [15:0]  data_xi;
   bit [15:0]  data_xq;

基本随机函数:

   //function my_randomize
   function int my_randomize(int seed);
       int temp1, temp2;
       temp1 = (($urandom(seed)) + 1);
       data_xi = temp1 - 1;
       temp2 = (($urandom(seed)) + 1);
       data_xq = temp2 - 1;
       if(temp1 != 0 || temp2 != 0 )
         return 1;
       else
         return 0;
   endfunction: my_randomize

现在我必须将其更改为静态函数,其行为类似于

Now I have to change it to static function which suppose to behave like randomize() with constraints.

我该如何实现呢?

推荐答案

1)要使函数像约束一样,可以在函数中输入设置范围或取模。

1) To make your function like constraints, you can have inputs to your function to set the range or a modulo.

//function my_randomize
function int my_randomize(int seed, int temp1_min, int temp1_max, int temp2_min, int temp2_max, int temp3_min, int temp3_max);
    int temp1, temp2, temp3;
    temp1 = $urandom_range(temp1_min, temp1_max);
    temp2 = (($urandom(seed)) % (temp2_max+1));
    data_xi = temp2 - 1;
    temp3 = ((($urandom($urandom(seed))) % temp3_max+1) + temp3_min;
    data_xq = temp3 - 1;
    if(temp1 != 0 || temp2 != 0 )
      return 1;
    else
      return 0;
endfunction: my_randomize

当然,您可以决定如何对 temp1 temp2 temp3 。这些是一些想法。

Ofcourse you can decide how to implement the randomization for temp1, temp2 and temp3. These are some ideas.

2)如果希望所有类都访问此函数,请创建一个基类。使用随机化功能,然后从中派生所有类。尽管在这种情况下您将无法访问派生类变量,但只能访问基类变量。您始终可以将其设为要在派生类中覆盖的虚函数。

2) If you want all classes to access this function, create a base class with the randomize functionality, and then derive all your classes from it. Although you won't have access to the derived class variables in this case, just base-class variables. You can always make this a virtual function to override in your derived class.

3)注意,使用相同的 seed 在同一线程中为 $ urandom / $ urandom_range 创建相同的随机数。

3) Note that using the same seed for $urandom/$urandom_range in the same thread will create the same random number.

这篇关于系统Verilog-randomize()的实现的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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