错误 (10028):无法解析网络的多个常量驱动程序... VHDL 错误 [英] Error (10028): Can't resolve multiple constant drivers for net... VHDL ERROR
问题描述
我正在尝试编写一个代码，该代码将检测 din 信号的上升沿，并在此发生后提高 5 个时钟周期的 DOUT.我在编译时不断收到不同的错误，我不确定它们是什么意思.我想我对 VHDL 中的一些概念缺乏基本的了解，但可悲的是在网上查看并没有帮助我.我仍然没有感觉软件可以接受哪些操作.
I'm trying to write a code that will detect a rising edge on din signal and will raise dout for 5 clock cycles after that happens. I keep on getting different errors while compiling and I'm not sure what they mean. I think I lack a basic understanding of some concepts in VHDL but sadly looking online and did not help me much. I still don't have a feeling of what actions are acceptable by the software.
在我的代码中，我目前在第一个过程中有一个上升沿检测器，它将 dout 提升到逻辑高.第二个过程检查 dout 是否为高，然后从 5 倒数到 0，在 0 时将 dout 设置为逻辑低.
In my code I currently have a rising edge detector at the 1st process which raises dout to logic high. The second process checks if dout is high and while so counts down from 5 to 0 and on 0 sets dout to logic low.
这不会编译并返回以下错误:
This does not compile and returns the following errors:
错误 (10028):无法在rise_ext.vhd(31) 处为 net "count[2]" 解析多个常量驱动程序
Error (10028): Can't resolve multiple constant drivers for net "count[2]" at rise_ext.vhd(31)
错误 (10029):rise_ext.vhd(17) 处的恒定驱动程序
Error (10029): Constant driver at rise_ext.vhd(17)
错误 (10028):无法在rise_ext.vhd(31) 处为 net "count[1]" 解析多个常量驱动程序
Error (10028): Can't resolve multiple constant drivers for net "count[1]" at rise_ext.vhd(31)
错误 (10028):无法在rise_ext.vhd(31) 处为 net "count[0]" 解析多个常量驱动程序
Error (10028): Can't resolve multiple constant drivers for net "count[0]" at rise_ext.vhd(31)
错误 (10028):无法在rise_ext.vhd(31) 处为网络dout"解析多个常量驱动程序
Error (10028): Can't resolve multiple constant drivers for net "dout" at rise_ext.vhd(31)
错误 (10029):rise_ext.vhd(19) 处的恒定驱动程序
Error (10029): Constant driver at rise_ext.vhd(19)
错误 (12153):无法详细说明顶级用户层次结构
Error (12153): Can't elaborate top-level user hierarchy
错误:Quartus II 32-bit Analysis &合成失败.7 个错误，2 个警告错误:峰值虚拟内存:326 MB错误:处理结束:2014 年 1 月 11 日星期六 13:13:38错误:经过时间:00:00:04错误:总 CPU 时间(在所有处理器上):00:00:02
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 7 errors, 2 warnings Error: Peak virtual memory: 326 megabytes Error: Processing ended: Sat Jan 11 13:13:38 2014 Error: Elapsed time: 00:00:04 Error: Total CPU time (on all processors): 00:00:02
错误 (293001):Quartus II 完整编译失败.9 个错误，2 个警告
Error (293001): Quartus II Full Compilation was unsuccessful. 9 errors, 2 warnings
entity rise_ext is
port ( clk: in bit ;
resetN: in bit ;
din: in bit ;
count: buffer integer range 0 to 6 ;
dout: buffer bit ) ;
end rise_ext ;
architecture arc_rise_ext of rise_ext is
signal s1 , s2 : bit ;
begin
process ( resetN, clk )
begin
if resetN = '0' then
dout <= '0' ;
count <= 5 ;
elsif clk'event and clk = '1' then
s1 <= din ;
s2 <= s1 ;
dout <= not s1 and s2 ;
end if ;
end process ;
process ( clk, dout )
begin
if clk'event and clk = '1' then
if dout = '1' then
if count > 0 then
count <= count - 1 ;
else
dout <= '0' ;
count <= 5 ;
end if;
end if ;
end if ;
end process ;
end arc_rise_ext ;
任何帮助将不胜感激！
我将所有数据类型更改为 std_logic 并完成了代码，但仍然出现这些错误...
I changed all the data types to std_logic and finished the code, still I get these errors...
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rise_ext is
port ( clk: in std_logic ;
resetN: in std_logic ;
din: in std_logic ;
count: buffer integer range 0 to 6 ;
dout: buffer std_logic ) ;
end rise_ext ;
architecture arc_rise_ext of rise_ext is
signal s1 , s2 : std_logic ;
begin
process ( resetN, clk )
begin
if resetN = '0' then
dout <= '0' ;
count <= 6 ;
elsif rising_edge(clk) then
s1 <= din ;
s2 <= s1 ;
dout <= not s1 and s2 ;
end if ;
end process ;
process ( clk )
begin
if rising_edge(clk) then
if dout = '1' then
count <= 5 ;
end if ;
end if ;
end process ;
process ( clk )
begin
if rising_edge(clk) then
if count = 0 then
count <= 6 ;
dout <= '0' ;
else
count <= count - 1 ;
end if ;
end if ;
end process ;
end arc_rise_ext ;
推荐答案
您在两个进程中都分配了 dout 和 count.两者都不是解析信号.
You have dout and count assigned in both processes. Neither are resolved signals.
来自 IEEE 标准 1076-1993:
From IEEE Std 1076-1993:
12.6.1 驱动程序
12.6.1 Drivers
进程语句中的每个信号赋值语句都为某些标量信号定义了一组驱动程序.进程语句中的给定标量信号 S 有一个驱动程序，前提是该进程语句中至少有一个信号赋值语句，并且该信号赋值语句的目标信号的最长静态前缀表示 S 或表示一个S 是其子元素的复合信号.每个这样的信号赋值语句都被称为与该驱动程序相关联.信号赋值语句的执行仅影响相关的驱动程序.
Every signal assignment statement in a process statement defines a set of drivers for certain scalar signals. There is a single driver for a given scalar signal S in a process statement, provided that there is at least one signal assignment statement in that process statement and that the longest static prefix of the target signal of that signal assignment statement denotes S or denotes a composite signal of which S is a subelement. Each such signal assignment statement is said to be associated with that driver. Execution of a signal assignment statement affects only the associated driver(s).
这实质上意味着您正在复制 count 和 dout.
This essentially means you are duplicating both count and dout.
有很多方法可以对您想要的 dout 和 count 的行为进行建模.根据开始和结束事件将它们的操作分为两个过程不是其中之一.这将需要三个过程，一个用于创建事件，一个用于中断事件，另一个用于时钟存储.您可能需要单独的事件来操作 count.
There are many ways to model the behavior of dout and count you desire. Bifurcating their operation across two processes based on starting and ending events isn't one of them. That would require three processes, one for the making event, one for the breaking event and one for the clocked storage. You'd likely need separate events for operating count.
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