为什么我需要在其他架构中实例化 VHDL 组件之前重新声明它们? [英] Why do I need to redeclare VHDL components before instantiating them in other architectures?

问题描述

自从我上第一堂 VHDL 课以来，我就一直在挠头，并决定在这里发布我的问题.

I've been scratching my head since my first VHDL class and decided to post my question here.

鉴于我有一个声明的实体(以及它的架构)并想在另一个架构中实例化它，为什么我似乎必须在实例化它之前重新声明这个包含架构中的实体"(组件)?

Given that I have a declared entity (and also an architecture of it) and want to instantiate it inside another architecture, why is it that I seemingly have to redeclare the "entity" (component) inside this containing architecture before instantiating it?

编译器是否足够聪明，仅凭名称就可以将实例化与其架构相匹配?哪里需要组件声明?

Isn't the compiler smart enough to match an instantiation to its architecture just by its name? Where is the need for the component declaration?

推荐答案

如果需要，您可以直接实例化组件:

You can directly instantiate the component, if desired:

  MyInstantiatedEntity : entity work.MyEntity_E
    generic map (
        config          => whatever)
    port map (
        clk             => signal1,
        clk_vid         => signal2,
        ...

创建组件声明使您能够通过配置规范或类似规范更改绑定到实例化的内容.

Creating a component declaration gives you the extra ability to change what gets bound to the instantiation via a configuration specification or similar.

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