VHDL 类型转换 - 找到 4 种可能的定义 [英] VHDL type conversion - found 4 possible definitions

问题描述

我正在尝试将两个 std_logic 位转换为整数，如下所示

I am trying convert two std_logic bits to an integer as follows

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY TEST IS
    PORT (sw1, sw0  :   IN      std_logic;
          x         :   OUT     integer RANGE 3 DOWNTO 0);
END ENTITY TEST;

ARCHITECTURE dflow OF TEST IS
    SIGNAL mes_sel : integer RANGE 3 DOWNTO 0;
BEGIN
    mes_sel <= to_integer(unsigned(std_logic_vector(SW1 & SW0)));
    x <= mes_sel;
END ARCHITECTURE dflow;

但编译器不喜欢 mes_sel 赋值.我收到以下编译器错误消息:

but the compiler does not like the mes_sel assignment. I get the following compiler error message:

错误 (10327):Q4.vhd(92) 处的 VHDL 错误:无法确定运算符&"的定义 -- 找到 4 个可能的定义

Error (10327): VHDL error at Q4.vhd(92): can't determine definition of operator ""&"" -- found 4 possible definitions

我可以不将 2 位 std_logic 连接到一个向量然后转换吗?或者是别的什么?问候

Can I not concatenate 2 bit of std_logic to a vector and then convert? Or is it something else? regards D

推荐答案

错误信息大致告诉你哪里出了问题，不是赋值的问题.

The error message tells you roughly what's wrong, and it's not a problem with the assignment.

GHDL 给出了更好的诊断:

GHDL gives a better diagnosis:

ghdl -a test.vhd
test.vhd:13:57:无法解决运算符&"
的重载test.vhd:13:57:可能的解释是:
../../src/ieee/numeric_std.v93:66:18:数组类型签名"
../../src/ieee/numeric_std.v93:65:20:数组类型无符号"
../../src/ieee/std_logic_1164.v93:69:30:数组类型std_logic_vector"
../../src/ieee/std_logic_1164.v93:54:31:数组类型std_ulogic_vector"
ghdl:编译错误

ghdl -a test.vhd
test.vhd:13:57: can't resolve overload for operator "&"
test.vhd:13:57: possible interpretations are:
../../src/ieee/numeric_std.v93:66:18: array type "signed"
../../src/ieee/numeric_std.v93:65:20: array type "unsigned"
../../src/ieee/std_logic_1164.v93:69:30: array type "std_logic_vector"
../../src/ieee/std_logic_1164.v93:54:31: array type "std_ulogic_vector"
ghdl: compilation error

VHDL 允许重载运算符，可通过其参数类型(在本例中为 std_logic)和返回类型(在本例中......嗯......什么?)进行区分.

VHDL allows overloaded operators, distinguishable by the types of their arguments (in this case, std_logic) and their return types, (in this case ... well... what?)

显然有 4 种类型，它们声明了 std_logic_vector() 类型转换函数，以及带有两个 std_logic 参数的 & 运算符；和 ghdl(与您使用的任何工具不同)有助于列出它们.

There are apparently 4 types which have a std_logic_vector() type conversion function declared on them, as well as a & operator taking two std_logic arguments; and ghdl (unlike whatever tool you're using) helpfully lists them.

在这种情况下，VHDL(与其他一些语言不同)坚持让您选择一种，而不是随意为您做出隐藏的(可能是错误的)选择.

In such cases, VHDL (unlike some other languages) insists that you pick one, rather than arbitrarily making a hidden (and possibly wrong) choice for you.

您可以使用类型标记执行此操作.由于您实际上想要一个 unsigned，显而易见的选择是 unsigned'()(注意'"符号，也用于属性).

You can do this with a type mark. As you actually want an unsigned, the obvious choice is unsigned'() (note the "'" symbol, also used for attributes).

mes_sel <= to_integer(unsigned'(SW1 & SW0));

请注意，如果 VHDL 允许更简单的东西，例如 to_integer(SW1 & SW0)，那将是非常危险的，因为没有什么可区分有符号和无符号转换，使转换至少是非-很明显，而且很可能是错误的.

Note that if VHDL allowed anything simpler, like to_integer(SW1 & SW0) it would be positively dangerous as there is nothing to distinguish between signed and unsigned conversions, making the conversion at least non-obvious, and quite possibly wrong.

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