端口映射中的 VHDL 选择机器错误 [英] VHDL Selection machine error in port map

问题描述

我收到此错误:

# Error: COMP96_0100: data_reg.vhd : (156, 35): Actual parameter type in port map does not match the port formal type "Allin".
# Error: COMP96_0100: data_reg.vhd : (158, 1): Actual parameter type in port map does not match the port formal type "Fout".
# Error: COMP96_0100: data_reg.vhd : (162, 1): Actual parameter type in port map does not match the port formal type "D".
# Error: COMP96_0100: data_reg.vhd : (163, 1): Actual parameter type in port map does not match the port formal type "Q". 

我需要一些帮助，请.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ticket1 is
    port (
        A, B : in std_logic_vector(7 downto 0);
        Clock: in std_logic;
        O: out std_logic_vector(7 downto 0));
end entity;

architecture Ticketmachine of ticket1 is  

component ticket_selection 
    port(
        Allin:in bit_vector(3 downto 0);
        Clk: in std_logic;
        Fout: out bit_vector(7 downto 0));  
end component ticket_selection;

component  reg is  
    port(
        C: in std_logic;  
        D: in bit_vector(7 downto 0);
        Q : out bit_vector(7 downto 0));  
end component reg;        

component  Money is
    port (
        Ai,Bi : in std_logic_vector(7 downto 0);
        Fo: out std_logic_vector(7 downto 0));
end component money;

    signal s1,s2: std_logic_vector(7 downto 0);

begin 
    Option: ticket_selection
        port map(
            Allin=>A,
            Clk=>Clock,    
            Fout=>s1);

    Cash: reg
        port map(
            C=>Clock,
            D=>B,
            Q=>s2);

    Pros: Money
        port map(
            Ai=>s1,
            Bi=>s2,
            Fo=>O);
 end architecture;

推荐答案

你应该仔细阅读一些适合初学者的 VHDL 指南.我不能推荐任何(也许有人可以?)，所以我会在这里直接指出你的错误:

You should read carefully some VHDL guide for beginners. I can't recommend any (maybe someone could?), so I'll go straight to your mistakes here:

1. 切勿使用 std_logic_unsigned、std_logic_unsigned 和 std_logic_arith.这个库不是标准的一部分，可以用 numeric_std 替换.
2. 不要使用 bit 或 bit_vector 类型.改用 std_logic 和 std_logic_vector.
3. 当您将一个向量与另一个向量关联时，它们必须具有相同的类型和长度，正如 user1155120 和 Brian Drummond 在评论中所写.特别是，您不能将 std_logic_vector(7 downto 0) 分配给 bit_vector(3 downto 0).

1. Never use std_logic_unsigned, std_logic_unsigned, and std_logic_arith. This libraries are not part of standard, and can be replaced with numeric_std.
2. Don't use bit or bit_vector type. Use std_logic, and std_logic_vector instead.
3. When you associate one vector to other, they must have equal type and length, as user1155120 and Brian Drummond wrote in comment. In particular, you can't assign std_logic_vector(7 downto 0) to bit_vector(3 downto 0).

这里可能做错了更多的事情，但您的问题并不完整 - 您没有提供任何解释它应该做什么，没有完整的代码，也没有测试平台.

There are probably more things done wrong here, but your question is not complete - you didn't provide any explanation what it should do, no full code, and no testbench.

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