什么是存储缓冲区? [英] what is a store buffer?

问题描述

谁能解释什么是加载缓冲区以及它与失效队列有何不同.以及存储缓冲区和写入组合缓冲区之间的区别?保罗 E 麦肯尼的论文 http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf 很好地解释了存储缓冲区和失效队列，但不幸的是没有谈论写入组合缓冲区

can anyone explain what is load buffer and how it's different from invalidation queues. and also difference between store buffers and write combining buffers? The paper by Paul E Mckenny http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf explains very nicely about the store buffers and invalidation queues but unfortunately doesn't talk about write combining buffers

推荐答案

无效队列更像是存储缓冲区，但它是内存系统的一部分，而不是 CPU.基本上它是一个队列，用于跟踪失效并确保它们正确完成，以便缓存可以获取缓存行的所有权，然后它可以写入该行.加载队列是一种推测性结构，用于跟踪无序处理器中正在进行的加载.例如，可能出现以下情况

An invalidate queue is more like a store buffer, but it's part of the memory system, not the CPU. Basically it is a queue that keeps track of invalidations and ensures that they complete properly so that a cache can take ownership of a cache line so it can then write that line. A load queue is a speculative structure that keeps track of in-flight loads in the out of order processor. For example, the following can occur

1. CPU 推测性地从 X 发出负载
2. 那个加载是按程序顺序在存储到 Y 之后的，但 Y 的地址尚未解析，因此存储不会继续.
3. Y 已解析，结果等于 X.在解析 Y 的存储时，该存储在加载队列中搜索已发出的推测性加载，但在程序中存在于 Y 的存储之后命令.它会注意到 X 的负载(等于 Y)，并且必须压缩从负载 X 开始并跟随其后的那些指令.

1. CPU speculatively issue a load from X
2. That load was in program order after a store to Y, but the address of Y is not resolved yet, so the store does not proceed.
3. Y is resolved and it turns out to be equal to X. At the time that the store to Y is resolved, that store searches the load queue for speculative loads that have issued, but are present after the store to Y in program order. It will notice the load to X (which is equal to Y) and have to squash those instructions starting with load X and following.

存储缓冲区是存在于 CPU 中的一种推测结构，就像加载队列一样，用于允许 CPU 推测存储.写组合缓冲区是内存系统的一部分，本质上是将一堆小写(想想 8 字节写)打包成一个更大的事务(64 字节缓存行)，然后再将它们发送到内存系统.这些写入不是推测性的，并且是一致性协议的一部分.目标是节省总线带宽.通常，写入组合缓冲区用于对 I/O 设备(通常用于图形卡)的未缓存写入.在 I/O 设备中，通过执行 8 字节写入来对设备寄存器进行大量编程是很常见的，并且写入组合缓冲区允许将这些写入通过缓存传送出去时将它们组合成更大的事务.

A store buffer is a speculative structure that exists in the CPU, just like the load queue and is for allowing the CPU to speculate on stores. A write combining buffer is part of the memory system and essentially takes a bunch of small writes (think 8 byte writes) and packs them into a single larger transaction (a 64-byte cache line) before sending them to the memory system. These writes are not speculative and are part of the coherence protocol. The goal is to save bus bandwidth. Typically, a write combining buffer is used for uncached writes to I/O devices (often for graphics cards). It's typical in I/O devices to do a bunch of programming of device registers by doing 8 byte writes and the write combining buffer allows those writes to be combined into larger transactions when shipping them out past the cache.

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