TrustZone 监控模式和 IFAR、IFSR、DFAR、DFSR [英] TrustZone monitor mode and IFAR, IFSR, DFAR, DFSR
问题描述
ARM TrustZone 监控模式 可以捕获监控模式下的异常终止.监控模式始终在安全环境或上下文中执行.当它陷入监控模式instruction abort 和data fault 向量时,我们如何知道是什么地址和原因导致了正常世界中的故障?
The ARM TrustZone monitor mode can trap aborts in monitor mode. The monitor mode always executes in the secure world or context. How can we know what address and reason caused a fault in the normal world when it traps to the monitor mode instruction abort and data fault vectors?
IFSR
, IFAR
, DFSR
和 DFAR
是银行 CP15 寄存器.
推荐答案
值得注意的是,只有外部中止可以配置为监听模式,因此不会捕获 MMU 访问故障.
It is worth noting that only external aborts can be configured to be taken in monitor mode, so MMU access faults will not be trapped.
至于主要问题:所有安全/非安全存储寄存器的状态在监控模式下由 cp15 安全配置寄存器 NS 位的状态控制:当它被设置时,您访问非安全版本,并在明确时访问安全版本.
As for the main question: the state of all Secure/Non-secure banked registers while in monitor mode is controlled by the state of the cp15 Secure Configuration Register NS bit: when it is set, you access Non-secure versions, and when it is clear you access Secure versions.
以下是一些内联的 gcc
代码,它允许任何 secure world 模式检查这些 CP15
寄存器.
The following is some inline gcc
code which allows any secure world mode to inspect these CP15
registers.
#define MODE_MONITOR 0x16
unsigned int mode;
unsigned int world;
unsigned int dfar;
unsigned int dfsr;
unsigned int ifar;
unsigned int ifsr;
asm (" mrs %0, cpsr\n" /* Save mode. */
" mrc p15, 0, %1, c1, c1, 0\n"
" orr %1, %1, #1\n" /* Set NS bit in SCR. */
" cpsid aif, %6\n" /* To monitor mode... */
" mcr p15, 0, %1, c1, c1, 0\n"
" mrc p15, 0, %2, c6, c0, 0\n"
" mrc p15, 0, %3, c5, c0, 0\n"
" mrc p15, 0, %4, c6, c0, 2\n"
" mrc p15, 0, %5, c5, c0, 1\n"
" bic %1, %1, #1\n" /* Clear NS bit in SCR. */
" mcr p15, 0, %1, c1, c1, 0\n"
" isb\n"
" msr cpsr, %0\n"
: "=&r" (mode), "=&r" (world),
"=r"(dfar), "=r"(dfsr),
"=r"(ifar), "=r"(ifsr)
: "I" (MODE_MONITOR));
printf("DFAR: %.8x dfsr: %.8x IFAR: %.8x ifsr: %.8x\n",
dfar, dfsr, ifar, ifsr);
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