原子 x86 指令与 MS 的 InterlockedCompareExchange 文档的对齐要求? [英] Alignment requirements for atomic x86 instructions vs. MS's InterlockedCompareExchange documentation?

问题描述

Microsoft 提供了 InterlockedCompareExchange 用于执行原子比较和交换操作的函数.还有一个 _InterlockedCompareExchange 内在.

Microsoft offers the InterlockedCompareExchange function for performing atomic compare-and-swap operations. There is also an _InterlockedCompareExchange intrinsic.

在 x86 上，这些是使用 lock cmpxchg 指令实现的.

On x86 these are implemented using the lock cmpxchg instruction.

然而，通读关于这三种方法的文档，他们似乎在对齐要求上不一致.

However, reading through the documentation on these three approaches, they don't seem to agree on the alignment requirements.

英特尔的参考手册 没有提及对齐(除了那如果对齐检查已启用并且进行了未对齐的内存引用，则会生成异常)

Intel's reference manual says nothing about alignment (other than that if alignment checking is enabled and an unaligned memory reference is made, an exception is generated)

我还查找了 lock 前缀，它特别指出

I also looked up the lock prefix, which specifically states that

LOCK 前缀的完整性不受内存字段对齐的影响.

The integrity of the LOCK prefix is not affected by the alignment of the memory field.

(强调我的)

所以英特尔似乎说对齐是无关紧要的.无论如何操作都是原子的.

So Intel seems to say that alignment is irrelevant. The operation will be atomic no matter what.

_InterlockedCompareExchange 内在文档也没有说明对齐，但是 InterlockedCompareExchange function 指出

The _InterlockedCompareExchange intrinsic documentation also says nothing about alignment, however the InterlockedCompareExchange function states that

此函数的参数必须在 32 位边界上对齐；否则，该函数在多处理器 x86 系统和任何非 x86 系统上的行为将不可预测.

The parameters for this function must be aligned on a 32-bit boundary; otherwise, the function will behave unpredictably on multiprocessor x86 systems and any non-x86 systems.

那是什么?InterlockedCompareExchange 的对齐要求是否只是为了确保该函数即使在 cmpxchg 指令不可用的 486 之前的 CPU 上也能工作?根据上述信息，这似乎很可能，但我想在依赖它之前确定.:)

So what gives? Are the alignment requirements for InterlockedCompareExchange just to make sure the function will work even on pre-486 CPU's where the cmpxchg instruction isn't available? That seems likely based on the above information, but I'd like to be sure before I rely on it. :)

还是 ISA 需要对齐以保证原子性，而我只是在英特尔参考手册中查找了错误的地方?

Or is alignment required by the ISA to guarantee atomicity, and I'm just looking the wrong places in Intel's reference manuals?

推荐答案

您引用的 PDF 是 1999 年的，显然已经过时了.

The PDF you are quoting from is from 1999 and CLEARLY outdated.

最新的英特尔文档，特别是Volume-3A 讲述了一个不同的故事.

The up-to-date Intel documentation, specifically Volume-3A tells a different story.

例如，在 Core-i7 处理器上，您仍然必须确保您的数据不会跨越缓存行，否则无法保证操作是原子的.

For example, on a Core-i7 processor, you STILL have to make sure your data doesn't not span over cache-lines, or else the operation is NOT guaranteed to be atomic.

在 Volume 3A, System Programming, For x86/x64 Intel 明确指出:

On Volume 3A, System Programming, For x86/x64 Intel clearly states:

Intel486 处理器(以及后来的处理器)保证以下基本内存操作将始终以原子方式执行:

8.1.1 Guaranteed Atomic Operations

The Intel486 processor (and newer processors since) guarantees that the following basic memory operations will always be carried out atomically:

• 读取或写入一个字节
• 读取或写入以 16 位边界对齐的字
• 读取或写入在 32 位边界上对齐的双字

奔腾处理器(以及后来的处理器)保证以下额外的内存操作将始终以原子方式执行:

The Pentium processor (and newer processors since) guarantees that the following additional memory operations will always be carried out atomically:

• 读取或写入在 64 位边界上对齐的四字
• 对适合 32 位数据总线的未缓存内存位置的 16 位访问

P6 系列处理器(以及之后的更新处理器)保证以下额外的内存操作将始终以原子方式执行:

The P6 family processors (and newer processors since) guarantee that the following additional memory operation will always be carried out atomically:

• 对适合缓存的缓存内存的未对齐 16 位、32 位和 64 位访问线

对跨缓存行和页面边界分割的可缓存内存的访问Intel Core 2 Duo、Intel® Atom™、Intel Core 不保证是原子的Duo、奔腾 M、奔腾 4、英特尔至强、P6 系列、奔腾和英特尔 486 处理器.英特尔酷睿 2 双核、英特尔凌动、英特尔酷睿双核、奔腾 M、奔腾 4、英特尔至强、和 P6 系列处理器提供允许外部存储器的总线控制信号使拆分访问原子化的子系统；然而，非对齐的数据访问将严重影响处理器性能，应避免

Accesses to cacheable memory that are split across cache lines and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel® Atom™, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided

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