原子x86指令与MS的InterlockedCompareExchange文档的对齐要求? [英] Alignment requirements for atomic x86 instructions vs. MS's InterlockedCompareExchange documentation?

问题描述

Microsoft提供了 InterlockedCompareExchange 用于执行原子比较和交换操作的函数.还有一个 _InterlockedCompareExchange intrinsic .

Microsoft offers the InterlockedCompareExchange function for performing atomic compare-and-swap operations. There is also an _InterlockedCompareExchange intrinsic.

在x86上，这些是使用lock cmpxchg指令实现的.

On x86 these are implemented using the lock cmpxchg instruction.

但是，通读这三种方法的文档后，他们似乎对一致性要求并不一致.

However, reading through the documentation on these three approaches, they don't seem to agree on the alignment requirements.

Intel的参考手册关于对齐方式一无所知(除此之外如果启用对齐检查并进行未对齐的内存引用，则会生成异常)

Intel's reference manual says nothing about alignment (other than that if alignment checking is enabled and an unaligned memory reference is made, an exception is generated)

我还查询了lock前缀，该前缀具体说明了

I also looked up the lock prefix, which specifically states that

LOCK前缀的完整性不受的影响，不受内存字段对齐的影响.

The integrity of the LOCK prefix is not affected by the alignment of the memory field.

(重点是我的)

因此，英特尔似乎说对齐是无关紧要的.无论如何，该操作都是原子操作.

So Intel seems to say that alignment is irrelevant. The operation will be atomic no matter what.

_InterlockedCompareExchange内在文档也没有提及对齐，但是InterlockedCompareExchange 函数指出

The _InterlockedCompareExchange intrinsic documentation also says nothing about alignment, however the InterlockedCompareExchange function states that

此函数的参数必须在32位边界上对齐；否则，该功能将在多处理器x86系统和任何非x86系统上无法正常运行.

The parameters for this function must be aligned on a 32-bit boundary; otherwise, the function will behave unpredictably on multiprocessor x86 systems and any non-x86 systems.

那有什么用呢? InterlockedCompareExchange的对齐要求仅仅是为了确保即使在cmpxchg指令不可用的486之前版本的CPU上该功能也可以工作吗? 基于以上信息，这似乎很可能，但是我想在确定之前先确定一下. :)

So what gives? Are the alignment requirements for InterlockedCompareExchange just to make sure the function will work even on pre-486 CPU's where the cmpxchg instruction isn't available? That seems likely based on the above information, but I'd like to be sure before I rely on it. :)

还是ISA需要对齐才能保证原子性，而我只是在英特尔参考手册中找错地方了?

Or is alignment required by the ISA to guarantee atomicity, and I'm just looking the wrong places in Intel's reference manuals?

推荐答案

您引用的 PDF 是1999年的，显然已经过时了.

The PDF you are quoting from is from 1999 and CLEARLY outdated.

最新的英特尔文档，特别是

The up-to-date Intel documentation, specifically Volume-3A tells a different story.

例如，在Core-i7处理器上，您仍然必须确保数据不跨越高速缓存行，否则，不能保证该操作是原子性的.

For example, on a Core-i7 processor, you STILL have to make sure your data doesn't not span over cache-lines, or else the operation is NOT guaranteed to be atomic.

对于第3A卷，系统编程，对于x86/x64，英特尔明确声明:

On Volume 3A, System Programming, For x86/x64 Intel clearly states:

8.1.1保证原子操作

Intel486处理器(以及以后的较新处理器)保证了以下各项 基本的内存操作将始终以原子方式进行:

8.1.1 Guaranteed Atomic Operations

The Intel486 processor (and newer processors since) guarantees that the following basic memory operations will always be carried out atomically:

• 读取或写入字节
• 读取或写入在16位边界上对齐的单词
• 读取或写入在32位边界上对齐的双字

• Reading or writing a byte
• Reading or writing a word aligned on a 16-bit boundary
• Reading or writing a doubleword aligned on a 32-bit boundary

奔腾处理器(以及以后的较新处理器)保证了以下各项 额外的内存操作将始终以原子方式进行:

The Pentium processor (and newer processors since) guarantees that the following additional memory operations will always be carried out atomically:

• 读取或写入在64位边界上对齐的四字
• 16位访问适合32位数据总线的未缓存内存位置

P6系列处理器(以及以后的较新处理器)保证了以下各项 额外的内存操作将始终以原子方式进行:

The P6 family processors (and newer processors since) guarantee that the following additional memory operation will always be carried out atomically:

• 未对齐的16位，32位和64位对适合缓存的缓存的访问 线

• Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line

访问跨缓存行和页面边界划分的可缓存内存 Intel Core 2 Duo，Intel®Atom™，Intel Core不保证是原子的 Duo，Pentium M，Pentium 4，Intel Xeon，P6系列，Pentium和Intel486处理器. Intel Core 2 Duo，Intel Atom，Intel Core Duo，Pentium M，Pentium 4，Intel Xeon， 和P6系列处理器提供总线控制信号，以允许外部存储器 使分裂访问成为原子的子系统；但是，未对齐的数据访问将 严重影响处理器的性能，应避免

Accesses to cacheable memory that are split across cache lines and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel® Atom™, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided

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